From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 22:50:45 +0000 (-0700)
Subject: WIP for equivalency checking memories
X-Git-Tag: working-ls180~1084^2~21^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=698a0e3aafcae48535c68996fccf002c0e0e3aea;p=yosys.git

WIP for equivalency checking memories
---

diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
index fa5d004b0..9b7490cd8 100644
--- a/tests/ice40/memory.ys
+++ b/tests/ice40/memory.ys
@@ -1,5 +1,17 @@
 read_verilog memory.v
-synth_ice40
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
 cd top
 select -assert-count 1 t:SB_RAM40_4K
 select -assert-none t:SB_RAM40_4K %% t:* %D