From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 06:08:54 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~982
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=698b5ff8003394bf6dc122c28a0448daa18defb4;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 725b7430d..e56043312 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -22,7 +22,7 @@ The fundamentals are:
 In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source and destination have been "tagged" as Vectors, is simply:
 
     for i = 0 to VL-1:
-         GPR(RT+i) = GPR(RA+i) + GPR(RB+i))
+         GPR(RT+i) = GPR(RA+i) + GPR(RB+i)
 
 At its heart, SimpleV really is this simple.  On top of this fundamental basis further subtle refinements can be added which build up towards an extremrly powerful Vector augmentation system, with very little in the way of additional opcodes required.  RISC-V RVV as of version 0.9 is over 180 instructions: over 95% of rhat functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions.