From: lkcl <lkcl@web>
Date: Wed, 30 Dec 2020 18:55:56 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~693
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69905030908a50b1934faf4e4650d7c90d480d72;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 0469b3f07..b260c5909 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -485,10 +485,10 @@ destination, *all* the sequential ordered standard patterns of Vector
 ISAs are provided: VSPLAT, VSELECT, VINSERT, VCOMPRESS, VEXPAND.
 
 The only one missing from the list here, because it is non-sequential,
-is VGATHER: moving registers by specifying a vector of register indices
+is VGATHER (and VSCATTER): moving registers by specifying a vector of register indices
 (`regs[rd] = regs[regs[rs]]` in a loop).  This one is tricky because it
 typically does not exist in standard scalar ISAs.  If it did it would
-be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER.
+be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER/VSCATTER.
 
 # CR predicate result analysis