From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Sep 2020 11:49:49 +0000 (+0100)
Subject: add sys_rst to Clock Reset Generator
X-Git-Tag: 24jan2021_ls180~354
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6991f59619cefd42260ace8133d1bd2eda3ea4ba;p=soc.git

add sys_rst to Clock Reset Generator
---

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index ef7d4451..660760e6 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -129,7 +129,8 @@ class LibreSoCSim(SoCCore):
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
         # CRG -----------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("sys_clk"))
+        self.submodules.crg = CRG(platform.request("sys_clk"),
+                                  platform.request("sys_rst"))
 
         #ram_init = []