From: Eddie Hung Date: Mon, 1 Jul 2019 17:44:42 +0000 (-0700) Subject: Merge remote-tracking branch 'origin/master' into xaig_dff X-Git-Tag: working-ls180~881^2^2~291 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=699d8e393953a3e5f0c35afec54464e6810f8f1d;p=yosys.git Merge remote-tracking branch 'origin/master' into xaig_dff --- 699d8e393953a3e5f0c35afec54464e6810f8f1d diff --cc backends/aiger/xaiger.cc index 87dca014d,eb3d47569..8a35e06fa --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@@ -76,13 -88,10 +91,14 @@@ struct XAigerWrite dict aig_map; dict ordered_outputs; + dict ordered_latches; vector box_list; + bool omode = false; + //dict init_inputs; + //int initstate_ff = 0; + int mkgate(int a0, int a1) { aig_m++, aig_a++; @@@ -92,33 -101,40 +108,40 @@@ int bit2aig(SigBit bit) { - if (aig_map.count(bit) == 0) - { - aig_map[bit] = -1; - - if (not_map.count(bit)) { - int a = bit2aig(not_map.at(bit)) ^ 1; - aig_map[bit] = a; - } else - if (and_map.count(bit)) { - auto args = and_map.at(bit); - int a0 = bit2aig(args.first); - int a1 = bit2aig(args.second); - aig_map[bit] = mkgate(a0, a1); - } else - if (alias_map.count(bit)) { - aig_map[bit] = bit2aig(alias_map.at(bit)); - } + auto it = aig_map.find(bit); + if (it != aig_map.end()) { + log_assert(it->second >= 0); + return it->second; + } + + // NB: Cannot use iterator returned from aig_map.insert() + // since this function is called recursively + + int a = -1; + if (not_map.count(bit)) { + a = bit2aig(not_map.at(bit)) ^ 1; + } else + if (and_map.count(bit)) { + auto args = and_map.at(bit); + int a0 = bit2aig(args.first); + int a1 = bit2aig(args.second); + a = mkgate(a0, a1); + } else + if (alias_map.count(bit)) { + a = bit2aig(alias_map.at(bit)); + } - if (bit == State::Sx || bit == State::Sz) - log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n"); + if (bit == State::Sx || bit == State::Sz) { + log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n"); + a = aig_map.at(State::S0); } - log_assert(aig_map.at(bit) >= 0); - return aig_map.at(bit); + log_assert(a >= 0); + aig_map[bit] = a; + return a; } - XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module) + XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module) { pool undriven_bits; pool unused_bits; @@@ -586,10 -525,11 +634,16 @@@ aig_outputs.push_back(bit2aig(bit)); } + for (auto bit : ff_bits) { + aig_o++; + aig_outputs.push_back(ff_aig_map.at(bit)); + } ++ + if (output_bits.empty()) { + aig_o++; + aig_outputs.push_back(0); + omode = true; - } ++ } } void write_aiger(std::ostream &f, bool ascii_mode) @@@ -775,27 -691,9 +829,29 @@@ f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); f.write(buffer_str.data(), buffer_str.size()); + std::stringstream s_buffer; + auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1); + write_s_buffer(ff_bits.size()); + for (auto bit : ff_bits) { + auto it = bit.wire->attributes.find("\\init"); + if (it != bit.wire->attributes.end()) { + auto init = it->second[bit.offset]; + if (init == RTLIL::S1) { + write_s_buffer(1); + continue; + } + } + write_s_buffer(0); + } + f << "s"; + buffer_str = s_buffer.str(); + buffer_size_be = to_big_endian(buffer_str.size()); + f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + f.write(buffer_str.data(), buffer_str.size()); + if (holes_module) { + log_push(); + // NB: fixup_ports() will sort ports by name //holes_module->fixup_ports(); holes_module->check(); @@@ -915,11 -789,9 +973,13 @@@ for (auto &it : output_lines) f << it.second; log_assert(output_lines.size() == output_bits.size()); + if (omode && output_bits.empty()) + f << "output " << output_lines.size() << " 0 $__dummy__\n"; + latch_lines.sort(); + for (auto &it : latch_lines) + f << it.second; + wire_lines.sort(); for (auto &it : wire_lines) f << it.second; diff --cc frontends/aiger/aigerparse.cc index 60cbde857,1ac0f7ba4..7f81a4c89 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@@ -496,10 -506,11 +507,10 @@@ void AigerReader::parse_aiger_ascii( // Parse latches RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - log_assert(clk_name != ""); + if (L > 0 && !clk_name.empty()) { clk_wire = module->wire(clk_name); log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); + log_debug2("Creating %s\n", clk_name.c_str()); clk_wire = module->addWire(clk_name); clk_wire->port_input = true; clk_wire->port_output = false; @@@ -623,10 -631,11 +634,10 @@@ void AigerReader::parse_aiger_binary( // Parse latches RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - log_assert(clk_name != ""); + if (L > 0 && !clk_name.empty()) { clk_wire = module->wire(clk_name); log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); + log_debug2("Creating %s\n", clk_name.c_str()); clk_wire = module->addWire(clk_name); clk_wire->port_input = true; clk_wire->port_output = false; @@@ -730,53 -736,50 +741,59 @@@ void AigerReader::post_process() { - pool abc_carry_modules; + pool seen_boxes; - unsigned ci_count = 0, co_count = 0; + unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - if (seen_boxes.insert(cell->type).second) { + RTLIL::Module* flop_module = nullptr; + auto flop_module_name = box_module->attributes.at("\\abc_flop", RTLIL::Const()); + RTLIL::IdString flop_past_q; + if (flop_module_name.size() > 0) { + log_assert(flop_count < flopNum); + flop_module = design->module(RTLIL::escape_id(flop_module_name.decode_string())); + log_assert(flop_module); + flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string(); + } - else if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { - RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; - RTLIL::Wire* last_in = nullptr, *last_out = nullptr; - for (const auto &port_name : box_module->ports) { - RTLIL::Wire* w = box_module->wire(port_name); - log_assert(w); - if (w->port_input) { - if (w->attributes.count("\\abc_carry_in")) { - log_assert(!carry_in); - carry_in = w; ++ else if (seen_boxes.insert(cell->type).second) { + auto it = box_module->attributes.find("\\abc_carry"); + if (it != box_module->attributes.end()) { + RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; + auto carry_in_out = it->second.decode_string(); + auto pos = carry_in_out.find(','); + if (pos == std::string::npos) + log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); + auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos)); + carry_in = box_module->wire(carry_in_name); + if (!carry_in || !carry_in->port_input) + log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); + + auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1)); + carry_out = box_module->wire(carry_out_name); + if (!carry_out || !carry_out->port_output) + log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); + + auto &ports = box_module->ports; + for (auto jt = ports.begin(); jt != ports.end(); ) { + RTLIL::Wire* w = box_module->wire(*jt); + log_assert(w); + if (w == carry_in || w == carry_out) { + jt = ports.erase(jt); + continue; } - log_assert(!last_in || last_in->port_id < w->port_id); - last_in = w; + if (w->port_id > carry_in->port_id) + --w->port_id; + if (w->port_id > carry_out->port_id) + --w->port_id; + log_assert(w->port_input || w->port_output); + log_assert(ports[w->port_id-1] == w->name); + ++jt; } - if (w->port_output) { - if (w->attributes.count("\\abc_carry_out")) { - log_assert(!carry_out); - carry_out = w; - } - log_assert(!last_out || last_out->port_id < w->port_id); - last_out = w; - } - } - - if (carry_in != last_in) { - std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]); - std::swap(carry_in->port_id, last_in->port_id); - } - if (carry_out != last_out) { - log_assert(last_out); - std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]); - std::swap(carry_out->port_id, last_out->port_id); + ports.push_back(carry_in->name); + carry_in->port_id = ports.size(); + ports.push_back(carry_out->name); + carry_out->port_id = ports.size(); } } diff --cc passes/techmap/abc9.cc index f56350b1d,f107f9947..2eee43739 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@@ -498,15 -539,9 +542,15 @@@ void abc9_module(RTLIL::Design *design if (w->port_output) { RTLIL::Wire *wire = module->wire(w->name); log_assert(wire); - for (int i = 0; i < GetSize(wire); i++) + for (int i = 0; i < GetSize(w); i++) output_bits.insert({wire, i}); } + + auto jt = w->attributes.find("\\init"); + if (jt != w->attributes.end()) { + auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second)); + log_assert(r.second); + } } for (auto &it : module->connections_) { diff --cc techlibs/xilinx/Makefile.inc index 12ec20053,e9ea10e48..860fcd88c --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@@ -30,9 -30,10 +30,11 @@@ $(eval $(call add_share_file,share/xili $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) + +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) + $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --cc techlibs/xilinx/abc_xc7.box index 4caf69320,6dd71d758..bb9258e78 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@@ -37,26 -48,6 +48,26 @@@ RAM64X1D 5 0 15 # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO - RAM128X1D 5 0 17 2 - - - - - - - - - 314 314 314 314 314 314 292 - - - 347 347 347 347 347 347 296 - - - - - - - - - - + RAM128X1D 6 0 17 2 + - - - - - - - - 1009 998 839 774 605 494 450 - - + 1047 1036 877 812 643 532 478 - - - - - - - - - - + +# Inputs: C CE D R \$pastQ +# Outputs: Q +FDRE 6 1 5 1 +- 109 -46 358 0 + +# Inputs: C CE D S \$pastQ +# Outputs: Q +FDSE 7 0 5 1 +- 109 -46 358 0 + +# Inputs: C CE CLR D \$pastQ +# Outputs: Q +FDCE 8 0 5 1 +- 109 - -46 0 + +# Inputs: C CE D PRE \$pastQ +# Outputs: Q +FDPE 9 0 5 1 +- 109 -46 - 0 diff --cc techlibs/xilinx/synth_xilinx.cc index d3f096220,b7c32d2e0..cdc64db1d --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@@ -276,32 -285,35 +285,42 @@@ struct SynthXilinxPass : public ScriptP } if (check_label("map_cells")) { - if (abc == "abc9") - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); ++ if (abc9) + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -D _ABC -map +/xilinx/ff_map.v"); + else + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } if (check_label("map_luts")) { - if (abc == "abc9") { + run("opt_expr -mux_undef"); + if (help_mode) + run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')"); + else if (abc9) { + if (family != "xc7") + log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); + run("read_verilog -icells -lib +/xilinx/abc_ff.v"); - run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : "")); + if (nowidelut) + run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + else + run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + } + else { + if (nowidelut) + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); + else + run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); } - else if (help_mode) - run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); - else - run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - if (abc == "abc9") - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); ++ if (abc9) + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); + else + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean");