From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Sep 2022 11:03:14 +0000 (+0100)
Subject: add sv.isel asm-disasm tests to test_pysvp64dis.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69ab0fd0be302b3096e692d49af0e577c9df07fc;p=openpower-isa.git

add sv.isel asm-disasm tests to test_pysvp64dis.py
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 5f9cfc64..8a83c2ba 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -46,6 +46,15 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_3_sv_isel(self):
+        expected = [
+                    'sv.isel 12,2,3,33',
+                    'sv.isel 12,2,3,*33',
+                    'sv.isel 12,2,3,*483',
+                    'sv.isel 12,2,3,63',
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()