From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Wed, 7 Jun 2023 13:03:11 +0000 (+0000)
Subject: ls2: Added not about transistor count estimation.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69aeec94ab7e4e09c6cbae2ba9dd9e1853ee3dd2;p=libreriscv.git

ls2: Added not about transistor count estimation.
---

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index 50db6f876..3d8521dc7 100644
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -110,3 +110,15 @@ After that you can compile microwatt-verilator:
 
 	export FPGA_TARGET=verilator
 	make microwatt-verilator
+
+# Estimating transistor count using yosys
+
+Use yosys to run synthesis and using `stat` to view gate/transistor count:
+
+    cd src/ls2/
+    yosys
+    yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
+    yosys> synth
+    yosys> tee -a stat_cmos.log stat -tech cmos
+
+Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**