From: lkcl <lkcl@web>
Date: Thu, 20 Oct 2022 21:58:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69b70c2c95d9337d8dc7d15f490796ad8b9aff3d;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 2fbbf6dda..261013339 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -99,10 +99,10 @@ Add the following entries to:
 Pseudocode:
 
 ```
-    prod[0:127] <- (RA) * (RB)	  # Multiply RA and RB, result 128-bit
-    sum[0:127] <- EXTZ(RC) + prod # Zero extend RC, add product
-    RT <- sum[64:127]		  # Store low half in RT
-    RS <- sum[0:63] 		  # RS implicit register, equal to RC
+prod[0:127] <- (RA) * (RB)    # Multiply RA and RB, result 128-bit
+sum[0:127] <- EXTZ(RC) + prod # Zero extend RC, add product
+RT <- sum[64:127]             # Store low half in RT
+RS <- sum[0:63]               # RS implicit register, equal to RC
 ```
 
 Special registers altered:
@@ -155,16 +155,18 @@ maddedu r4, r0, r1, r2
 
 Pseudo-code:
 
-    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then   # Check RA<RB, for divide-by-0
-        dividend[0:(XLEN*2)-1] <- (RA) || (RC)    # Combine RA/RC, zero extend
-        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB) # Extend to 128-bit
-        result <- dividend / divisor		  # Division
-        modulo <- dividend % divisor		  # Modulo
-        RT <- result[XLEN:(XLEN*2)-1]		  # Store result in RT
-        RS <- modulo[XLEN:(XLEN*2)-1]		  # Modulo in RC, implicit
-    else					  # In case of error
-        RT <- [1]*XLEN				  # RT all 1's
-        RS <- [0]*XLEN				  # RS all 0's
+```
+if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then   # Check RA<RB, for divide-by-0
+    dividend[0:(XLEN*2)-1] <- (RA) || (RC)    # Combine RA/RC, zero extend
+    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB) # Extend to 128-bit
+    result <- dividend / divisor		  # Division
+    modulo <- dividend % divisor		  # Modulo
+    RT <- result[XLEN:(XLEN*2)-1]		  # Store result in RT
+    RS <- modulo[XLEN:(XLEN*2)-1]		  # Modulo in RC, implicit
+else					  # In case of error
+    RT <- [1]*XLEN				  # RT all 1's
+    RS <- [0]*XLEN				  # RS all 0's
+```
 
 Special registers altered:
 
@@ -190,8 +192,7 @@ zeros on overflow.
 instructions. `cmpi` will need to be used to detect overflow conditions:
 the saving in instruction count is that both RT and RS will have already
 been set to useful values (all 1s and all zeros respectively)
-needed as part of implementing Knuth's
-Algorithm D*
+needed as part of implementing Knuth's Algorithm D*
 
 For Scalar usage, just as for `maddedu`, `RS=RC`
 Examples: