From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Sat, 22 May 2021 16:18:50 +0000 (+0200)
Subject: Reject wide ports in some passes that will never support them.
X-Git-Tag: yosys-0.10~178
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69bf5c81c7cf65ccb8bd035eb45137e31a68ae86;p=yosys.git

Reject wide ports in some passes that will never support them.
---

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index bc0504d64..999836882 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -728,10 +728,19 @@ struct BtorWorker
 				log_error("Memory %s.%s has mixed async/sync write ports.\n",
 						log_id(module), log_id(mem->memid));
 
-			for (auto &port : mem->rd_ports)
+			for (auto &port : mem->rd_ports) {
 				if (port.clk_enable)
-					log_error("Memory %s.%s has sync read ports.\n",
+					log_error("Memory %s.%s has sync read ports.  Please use memory_nordff to convert them first.\n",
+							log_id(module), log_id(mem->memid));
+				if (port.wide_log2)
+					log_error("Memory %s.%s has wide read ports.  Please use memory_narrow to convert them first.\n",
+							log_id(module), log_id(mem->memid));
+			}
+			for (auto &port : mem->wr_ports) {
+				if (port.wide_log2)
+					log_error("Memory %s.%s has wide write ports.  Please use memory_narrow to convert them first.\n",
 							log_id(module), log_id(mem->memid));
+			}
 
 			int data_sid = get_bv_sid(mem->width);
 			int bool_sid = get_bv_sid(1);
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index f99becacf..dee24d0e2 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -993,6 +993,8 @@ struct FirrtlWorker
 
 				if (port.clk_enable)
 					log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
+				if (port.wide_log2 != 0)
+					log_error("Wide read port %d on memory %s.%s.  Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
 
 				std::ostringstream rpe;
 
@@ -1014,6 +1016,8 @@ struct FirrtlWorker
 
 				if (!port.clk_enable)
 					log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
+				if (port.wide_log2 != 0)
+					log_error("Wide write port %d on memory %s.%s.  Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
 				if (!port.clk_polarity)
 					log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
 				for (int i = 1; i < GetSize(port.en); i++)
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index e0f43d686..4dee0d4fb 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -715,6 +715,12 @@ struct Smt2Worker
 					has_sync_wr = true;
 				else
 					has_async_wr = true;
+				if (port.wide_log2)
+					log_error("Memory %s.%s has wide write ports. This is not supported by \"write_smt2\".  Use memory_narrow to convert them first.\n", log_id(cell), log_id(module));
+			}
+			for (auto &port : mem->rd_ports) {
+				if (port.wide_log2)
+					log_error("Memory %s.%s has wide read ports. This is not supported by \"write_smt2\".  Use memory_narrow to convert them first.\n", log_id(cell), log_id(module));
 			}
 			if (has_async_wr && has_sync_wr)
 				log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index c6948fdba..a860fc693 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1057,6 +1057,20 @@ void handle_memory(Mem &mem, const rules_t &rules)
 		log(" %s=%d", it.first.c_str(), it.second);
 	log("\n");
 
+	for (auto &port : mem.rd_ports) {
+		if (port.wide_log2) {
+			log("Wide read ports are not supported, skipping.\n");
+			return;
+		}
+	}
+
+	for (auto &port : mem.wr_ports) {
+		if (port.wide_log2) {
+			log("Wide write ports are not supported, skipping.\n");
+			return;
+		}
+	}
+
 	pool<pair<IdString, int>> failed_brams;
 	dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;