From: Luke Kenneth Casson Leighton Date: Thu, 2 Apr 2020 14:41:14 +0000 (+0100) Subject: missing whitespace X-Git-Tag: convert-csv-opcode-to-binary~2990 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69c47c553e6b0604e6de4e0aacf923056bc960b4;p=libreriscv.git missing whitespace --- diff --git a/openpower/isa/condition.mdwn b/openpower/isa/condition.mdwn index 65b7da067..c886a7a28 100644 --- a/openpower/isa/condition.mdwn +++ b/openpower/isa/condition.mdwn @@ -7,6 +7,7 @@ crand BT,BA,BB CR[BT+32] <- CR[BA+32] & CR[BB+32] Special Registers Altered: + CR[BT+32] # Condition Register NAND @@ -18,6 +19,7 @@ XL-Form CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32]) Special Registers Altered: + CR[BT+32] # Condition Register OR @@ -29,6 +31,7 @@ XL-Form CR[BT+32] <- CR[BA+32] | CR[BB+32] Special Registers Altered: + CR[BT+32] # Condition Register XOR @@ -40,6 +43,7 @@ XL-Form CR[BT+32] <- CR[BA+32] ^ CR[BB+32] Special Registers Altered: + CR[BT+32] # Condition Register NOR @@ -51,6 +55,7 @@ XL-Form CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32]) Special Registers Altered: + CR[BT+32] # Condition Register Equivalent @@ -62,6 +67,7 @@ XL-Form CR[BT+32] <- CR[BA+32] => CR[BB+32] Special Registers Altered: + CR[BT+32] # Condition Register AND with Complement @@ -73,6 +79,7 @@ XL-Form CR[BT+32] <- CR[BA+32] & ¬CR[BB+32] Special Registers Altered: + CR[BT+32] # Condition Register OR with Complement @@ -92,5 +99,6 @@ XL-Form CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35] Special Registers Altered: + CR field BF