From: lkcl <lkcl@web>
Date: Tue, 3 Aug 2021 09:08:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~520
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69c8e48baf35c07930c96566dd2c062b96b6d302;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index dfa2ecda0..3541d389a 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -209,3 +209,43 @@ Pseudocode for Vertical-First Mode:
             SVSTATE.VL = new_srcstep
     SVSTATE.srcstep = new_srcstep
 ```
+
+# Example Shader code
+
+```
+while(a > 2) {
+    if(b < 5)
+        f();
+    else
+        g();
+    h();
+}
+```
+
+which compiles to something like:
+
+```
+vec<i32> a, b;
+// ...
+pred loop_pred = a > 2;
+while(loop_pred.any()) {
+    pred if_pred = loop_pred & (b < 5);
+    if(if_pred.any()) {
+        f(if_pred);
+    }
+label1:
+    pred else_pred = loop_pred & ~if_pred;
+    if(else_pred.any()) {
+        g(else_pred);
+    }
+    h(loop_pred);
+}
+```
+
+which will end up as:
+
+```
+   sv.cmpi CR0, a, 2
+   sv.crweird r30, CR0.GT # transfer GT vector to r30
+while_loop:
+```