From: Cesar Philippidis Date: Mon, 17 Sep 2018 19:59:19 +0000 (-0700) Subject: [nvptx] Add atomic_fetch* support for SImode arguments. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69d7aabfd8fec442047cefb136b1fd2680310fa9;p=gcc.git [nvptx] Add atomic_fetch* support for SImode arguments. gcc/ * config/nvptx/nvptx.md (atomic_fetch_): Enable with SImode args. gcc/testsuite/ * gcc.target/nvptx/atomic-fetch-2.c: Rename to ... * gcc.target/nvptx/atomic_fetch-2.c: ... this. * gcc.target/nvptx/atomic_fetch-3.c: New test. Co-Authored-By: Bernd Schmidt From-SVN: r264371 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a9e05898ab9..017aa6446cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-09-17 Cesar Philippidis + Bernd Schmidt + + * config/nvptx/nvptx.md (atomic_fetch_): Enable with + SImode args. + 2018-09-17 Uros Bizjak * config/i386/i386.md (truncxf2_i387_noop_unspec): Change diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index dd6032d021b..ca00b1d8073 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -1449,7 +1449,7 @@ UNSPECV_LOCK)) (set (match_operand:SDIM 0 "nvptx_register_operand" "=R") (match_dup 1))] - "TARGET_SM35" + "mode == SImode || TARGET_SM35" "%.\\tatom%A1.b%T0.\\t%0, %1, %2;" [(set_attr "atomic" "true")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5cce863e58a..ddf5f730e79 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2018-09-17 Cesar Philippidis + Bernd Schmidt + + * gcc.target/nvptx/atomic-fetch-2.c: Rename to ... + * gcc.target/nvptx/atomic_fetch-2.c: ... this. + * gcc.target/nvptx/atomic_fetch-3.c: New test. + 2018-09-17 Richard Biener PR tree-optimization/87328 diff --git a/gcc/testsuite/gcc.target/nvptx/atomic-fetch-2.c b/gcc/testsuite/gcc.target/nvptx/atomic-fetch-2.c deleted file mode 100644 index 1d35a176a62..00000000000 --- a/gcc/testsuite/gcc.target/nvptx/atomic-fetch-2.c +++ /dev/null @@ -1,24 +0,0 @@ -/* Test the nvptx atomic instructions for __atomic_fetch_OP for SM_30 - targets. */ - -/* { dg-do compile } */ -/* { dg-options "-O2 -misa=sm_30" } */ - -int -main() -{ - unsigned long long a = ~0; - unsigned b = 0xa; - - __atomic_fetch_add (&a, b, 0); - __atomic_fetch_and (&a, b, 0); - __atomic_fetch_or (&a, b, 0); - __atomic_fetch_xor (&a, b, 0); - - return a; -} - -/* { dg-final { scan-assembler-not "atom.b64.add" } } */ -/* { dg-final { scan-assembler-not "atom.b64.and" } } */ -/* { dg-final { scan-assembler-not "atom.b64.or" } } */ -/* { dg-final { scan-assembler-not "atom.b64.xor" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/atomic_fetch-2.c b/gcc/testsuite/gcc.target/nvptx/atomic_fetch-2.c new file mode 100644 index 00000000000..1d35a176a62 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/atomic_fetch-2.c @@ -0,0 +1,24 @@ +/* Test the nvptx atomic instructions for __atomic_fetch_OP for SM_30 + targets. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -misa=sm_30" } */ + +int +main() +{ + unsigned long long a = ~0; + unsigned b = 0xa; + + __atomic_fetch_add (&a, b, 0); + __atomic_fetch_and (&a, b, 0); + __atomic_fetch_or (&a, b, 0); + __atomic_fetch_xor (&a, b, 0); + + return a; +} + +/* { dg-final { scan-assembler-not "atom.b64.add" } } */ +/* { dg-final { scan-assembler-not "atom.b64.and" } } */ +/* { dg-final { scan-assembler-not "atom.b64.or" } } */ +/* { dg-final { scan-assembler-not "atom.b64.xor" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/atomic_fetch-3.c b/gcc/testsuite/gcc.target/nvptx/atomic_fetch-3.c new file mode 100644 index 00000000000..36a83ebba9b --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/atomic_fetch-3.c @@ -0,0 +1,24 @@ +/* Test the nvptx atomic instructions for __atomic_fetch_OP for + SImode arguments. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -m32" } */ + +int +main() +{ + unsigned long a = ~0; + unsigned b = 0xa; + + __atomic_fetch_add (&a, b, 0); + __atomic_fetch_and (&a, b, 0); + __atomic_fetch_or (&a, b, 0); + __atomic_fetch_xor (&a, b, 0); + + return a; +} + +/* { dg-final { scan-assembler "atom.add.u32" } } */ +/* { dg-final { scan-assembler "atom.b32.and" } } */ +/* { dg-final { scan-assembler "atom.b32.or" } } */ +/* { dg-final { scan-assembler "atom.b32.xor" } } */