From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Dec 2021 13:38:37 +0000 (+0000)
Subject: fake up wishbone stall signal in icache.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69d89a02bda88cbece9d92a274b441c558c431a8;p=soc.git

fake up wishbone stall signal in icache.
same thing is done in dcache
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index f8477562..cf95633f 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -834,6 +834,10 @@ class ICache(Elaboratable):
         plru_victim      = PLRUOut()
         replace_way      = Signal(WAY_BITS)
 
+        # fake-up the wishbone stall signal to comply with pipeline mode
+        # same thing is done in dcache.py
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
+
         # call sub-functions putting everything together,
         # using shared signals established above
         self.rams(m, r, cache_out_row, use_previous, replace_way, req_row)