From: lkcl <lkcl@web>
Date: Thu, 27 Jun 2019 22:19:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4376
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69e5334183da058d8d5f7b13620c8ce09270d937;p=libreriscv.git

---

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index c0edc7beb..6d707b5ed 100644
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -270,6 +270,13 @@ like Standard RISC-V as far as the instruction execution order is
 concerned, regardless of whether it is PC, PCVBLK, VL or SUBVL that
 is currently being incremented.
 
+This.is extremely important. Exceptions
+**MUST** be raised one at a time and in
+strict sequential program order.
+
+No instructions are permitted to be out of
+sequence, therefore no exceptions are permitted to be, either.
+
 # Hints
 
 With Simple-V being capable of issuing *parallel* instructions where