From: lkcl <lkcl@web>
Date: Wed, 11 Sep 2019 00:24:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4116
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69e74771924b8d4e004daa45bc83c0cc964b3d94;p=libreriscv.git

---

diff --git a/ztrans_proposal.mdwn b/ztrans_proposal.mdwn
index 11e401bcd..757cfcb55 100644
--- a/ztrans_proposal.mdwn
+++ b/ztrans_proposal.mdwn
@@ -94,6 +94,9 @@ covered by Supercomputer Vectorisation Standards (such as RVV).
 
 **The "contra"-requirements are**:
 
+* NOT for use with RVV (RISC-V Vector Extension). These are *scalar* opcodes.
+  Ultra Low Power Embedded platforms (smart watches) are sufficiently resource constrained that Vectorisation
+  (of any kind) is likely to be unnecessary and inappropriate.
 * The requirements are **not** for the purposes of developing a full custom
   proprietary GPU with proprietary firmware
   driven by *hardware* centric optimised design decisions as a priority over collaboration.