From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2013 18:11:53 +0000 (+0100)
Subject: Collect parameters in hierarchy -generate (and do nothing with them)
X-Git-Tag: yosys-0.2.0~678
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a231816fa87f767eda2837faea838a57722e481;p=yosys.git

Collect parameters in hierarchy -generate (and do nothing with them)
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 04274990d..8ef169ce9 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -50,17 +50,21 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 	for (auto &celltype : found_celltypes)
 	{
 		std::set<std::string> portnames;
+		std::set<std::string> parameters;
 		std::map<std::string, int> portwidths;
 		log("Generate module for cell type %s:\n", celltype.c_str());
 
 		for (auto i1 : design->modules)
 		for (auto i2 : i1.second->cells)
-			if (i2.second->type == celltype)
+			if (i2.second->type == celltype) {
 				for (auto &conn : i2.second->connections) {
 					if (conn.first[0] != '$')
 						portnames.insert(conn.first);
 					portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
 				}
+				for (auto &para : i2.second->parameters)
+					parameters.insert(para.first);
+			}
 
 		for (auto &decl : portdecls)
 			if (decl.index > 0)
@@ -121,6 +125,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			mod->add(wire);
 		}
 
+		for (auto &para : parameters)
+			log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
+
 		log("  module %s created.\n", RTLIL::id2cstr(mod->name));
 	}
 }