From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Feb 2016 07:59:57 +0000 (+0100)
Subject: Bugfix in Verific front-end
X-Git-Tag: yosys-0.6~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a27cbe5b17b012aef904bc31c13d8a2b0b15f01;p=yosys.git

Bugfix in Verific front-end
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1ec6a7c0a..d2440f699 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -773,8 +773,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 			}
 			IdString port_name_id = RTLIL::escape_id(port_name);
 			auto &sigvec = cell_port_conns[port_name_id];
-			if (GetSize(sigvec) <= port_offset)
-				sigvec.resize(port_offset+1, State::Sz);
+			if (GetSize(sigvec) <= port_offset) {
+				SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec));
+				for (auto bit : zwires)
+					sigvec.push_back(bit);
+			}
 			sigvec[port_offset] = net_map.at(pr->GetNet());
 		}