From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 9 Dec 2015 10:40:27 +0000 (+0100)
Subject: build/xilinx/vivado: use build_name as top in synth_design
X-Git-Tag: 24jan2021_ls180~2023
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a4e3bb5c06ff82be33116c25a48f68f69eed19d;p=litex.git

build/xilinx/vivado: use build_name as top in synth_design
---

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 032b78bb..f199c075 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -87,7 +87,7 @@ class XilinxVivadoToolchain:
 
         tcl.append("read_xdc {}.xdc".format(build_name))
         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
-        tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
+        tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
         tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
         tcl.append("place_design")