From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 00:46:26 +0000 (-0800)
Subject: sigmap(wire) should inherit port_output status of POs
X-Git-Tag: working-ls180~778^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a52897aeeff3e452884512470f21fa898b9e780;p=yosys.git

sigmap(wire) should inherit port_output status of POs
---

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ec242aa1f..982558fb2 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -20,6 +20,7 @@
 #include "kernel/register.h"
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
+#include "kernel/sigtools.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <set>
@@ -32,6 +33,7 @@ struct SubmodWorker
 	CellTypes ct;
 	RTLIL::Design *design;
 	RTLIL::Module *module;
+	pool<Wire*> outputs;
 
 	bool copy_mode;
 	std::string opt_name;
@@ -125,7 +127,7 @@ struct SubmodWorker
 
 			if (wire->port_input)
 				flags.is_ext_driven = true;
-			if (wire->port_output)
+			if (wire->port_output || outputs.count(wire))
 				flags.is_ext_used = true;
 
 			bool new_wire_port_input = false;
@@ -219,6 +221,22 @@ struct SubmodWorker
 		ct.setup_stdcells_mem();
 		ct.setup_design(design);
 
+		SigMap sigmap(module);
+		for (auto port : module->ports) {
+			auto wire = module->wire(port);
+			if (!wire->port_output)
+				continue;
+			auto sig = sigmap(wire);
+			for (auto c : sig.chunks()) {
+				if (!c.wire)
+					continue;
+				if (c.wire == wire)
+					continue;
+				outputs.insert(c.wire);
+				log_dump(c.wire->name);
+			}
+		}
+
 		if (opt_name.empty())
 		{
 			for (auto &it : module->wires_)