From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Jun 2019 10:06:07 +0000 (+0200)
Subject: Add proper test for SV-style arrays
X-Git-Tag: yosys-0.9~64^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a6dd5e0575950174e3abde7a13a3e3be73e5299;p=yosys.git

Add proper test for SV-style arrays

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv
new file mode 100644
index 000000000..76c2a7388
--- /dev/null
+++ b/tests/simple/arrays02.sv
@@ -0,0 +1,16 @@
+module uut_arrays02(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [16];
+
+always @(posedge clock) begin
+	if (we)
+		memory[addr] <= wr_data;
+	rd_data <= memory[addr];
+end
+
+endmodule
diff --git a/tests/various/unpacked_arrays.sv b/tests/various/unpacked_arrays.sv
deleted file mode 100644
index 2f4ed0d3f..000000000
--- a/tests/various/unpacked_arrays.sv
+++ /dev/null
@@ -1,4 +0,0 @@
-module unpacked_arrays;
-  reg array_range [0:7];
-  reg array_size [8];
-endmodule
diff --git a/tests/various/unpacked_arrays.ys b/tests/various/unpacked_arrays.ys
deleted file mode 100644
index 419152d9c..000000000
--- a/tests/various/unpacked_arrays.ys
+++ /dev/null
@@ -1,2 +0,0 @@
-read_verilog -sv unpacked_arrays.sv
-stat