From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Jul 2022 13:09:32 +0000 (+0100)
Subject: redo numbering
X-Git-Tag: opf_rfc_ls005_v1~1142
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a765082ec14060f8e5b4e02ba6377a87bb51791;p=libreriscv.git

redo numbering
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 16f0edfd6..e2db33379 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,19 +1,20 @@
 # ISA Comparison Table
 
-| Name | Num <br />opcodes | Scalable | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
-|------|-------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
-| SVP64| 5{1}              | yes      | yes                    | yes{2}                  | no{3}                        | n/a{4}  | yes{5}                   | yes{6}                  | yes{7}                           | yes{8}                  |
-| VSX  | 700+              | no       | no                     | no                      | yes{9}                       | yes     | no                       | no                      | no                               | no                      |
-| NEON | ~250[10]          | no       | yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
+| Name | Num <br />opcodes | Class         | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
+|------|-------------------|---------------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
+| SVP64| 5{1}              | Scalable{2}   | yes                    | yes{3}                  | no{4}                        | n/a{5}  | yes{6}                   | yes{7}                  | yes{8}                           | yes{9}                  |
+| VSX  | 700+              | PackedSIMD    | no                     | no                      | yes{10}                      | yes     | no                       | no                      | no                               | no                      |
+| NEON | ~250{11}          | PredicatedSIMD| yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
 
 * {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]]
-* {2}: on specific operations.  See [[opcode_regs_deduped]]
-* {3}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files
-* {4}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit.
-* {5}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
-* {6} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
-* {7} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
-* {8} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
-* {9} VSX's Vector Registers are mis-named: they are PackedSIMD.
-* {10} difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions).
+* {2}: A 2-Dimensional Scalable Vector ISA with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
+* {3}: on specific operations.  See [[opcode_regs_deduped]] for full list
+* {4}: SVP64 provides the Vector register concept on top of the **Scalar** GPR, FPR and CR register files.
+* {5}: SVP64 Vectorises Scalar instructions. If (**optionally**) applied to e.g. VSX Quad-Precision instructions, SVP64 "becomes" 128-bit.
+* {6}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
+* {7} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
+* {8} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
+* {9} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
+* {10} VSX's Vector Registers are mis-named: they are PackedSIMD.
+* {11} difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions).
        critically depends on ARM Scalar instructions