From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 14 Dec 2014 20:03:14 +0000 (+0100)
Subject: command: fix TX path with random acknowledge
X-Git-Tag: 24jan2021_ls180~2572^2~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a783ad291e2bc6283f31434d714bf8a5c2a7383;p=litex.git

command: fix TX path with random acknowledge
---

diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py
index a669a2a1..c2ad667e 100644
--- a/lib/sata/command/__init__.py
+++ b/lib/sata/command/__init__.py
@@ -55,7 +55,7 @@ class SATACommandTX(Module):
 			)
 		)
 		fsm.act("SEND_WRITE_DMA_CMD",
-			transport.sink.stb.eq(1),
+			transport.sink.stb.eq(sink.stb),
 			transport.sink.sop.eq(1),
 			transport.sink.eop.eq(1),
 			transport.sink.type.eq(fis_types["REG_H2D"]),
diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py
index bd509277..afbe95dd 100644
--- a/lib/sata/test/command_tb.py
+++ b/lib/sata/test/command_tb.py
@@ -106,7 +106,7 @@ class TB(Module):
 	def __init__(self):
 		self.submodules.hdd = HDD(
 				phy_debug=False,
-				link_random_level=25, link_debug=False,
+				link_random_level=50, link_debug=False,
 				transport_debug=False, transport_loopback=False,
 				command_debug=False,
 				hdd_debug=True)
@@ -115,10 +115,10 @@ class TB(Module):
 		self.submodules.command = SATACommand(self.transport)
 
 		self.submodules.streamer = CommandStreamer()
-		streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=0)
+		streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=50)
 		self.submodules += streamer_ack_randomizer
 		self.submodules.logger = CommandLogger()
-		logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=25)
+		logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=50)
 		self.submodules += logger_ack_randomizer
 		self.comb += [
 			Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py
index 224171d5..92828d1e 100644
--- a/lib/sata/transport/__init__.py
+++ b/lib/sata/transport/__init__.py
@@ -54,13 +54,13 @@ class SATATransportTX(Module):
 					sink.ack.eq(1)
 				)
 			).Else(
-				sink.ack.eq(1)
+				sink.ack.eq(sink.stb)
 			)
 		)
 		fsm.act("SEND_REG_H2D_CMD",
 			_encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
 			cmd_len.eq(fis_reg_h2d_cmd_len-1),
-			cmd_send.eq(sink.stb),
+			cmd_send.eq(1),
 			If(cmd_done,
 				sink.ack.eq(1),
 				NextState("IDLE")
@@ -70,7 +70,7 @@ class SATATransportTX(Module):
 			_encode_cmd(sink, fis_data_layout, encoded_cmd),
 			cmd_len.eq(fis_data_cmd_len-1),
 			cmd_with_data.eq(1),
-			cmd_send.eq(sink.stb),
+			cmd_send.eq(1),
 			If(cmd_done,
 				NextState("SEND_DATA")
 			)
@@ -89,12 +89,12 @@ class SATATransportTX(Module):
 
 		self.comb += \
 			If(cmd_send,
-				link.sink.stb.eq(1),
+				link.sink.stb.eq(sink.stb),
 				link.sink.sop.eq(cnt==0),
 				link.sink.eop.eq((cnt==cmd_len) & ~cmd_with_data),
 				Case(cnt, cmd_cases),
-				inc_cnt.eq(link.sink.ack),
-				cmd_done.eq((cnt==cmd_len) & link.sink.ack)
+				inc_cnt.eq(sink.stb & link.sink.ack),
+				cmd_done.eq((cnt==cmd_len) & link.sink.stb & link.sink.ack)
 			).Elif(data_send,
 				link.sink.stb.eq(sink.stb),
 				link.sink.sop.eq(0),