From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 17:13:13 +0000 (-0700)
Subject: Update test with a/b reset
X-Git-Tag: working-ls180~1039^2~133
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a95ecd41d31a841537357a1ffaabf4ea5c7ed93;p=yosys.git

Update test with a/b reset
---

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index c6ad2a578..5dc99ab8e 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -61,10 +61,12 @@ always @(posedge clk) begin
 		// Store accumulation result into a register
 		adder_out <= adder_out + mult_reg;
 	end
-    if (rst) begin
+	if (rst) begin
+		a_reg <= 0;
+		b_reg <= 0;
 		mult_reg <= 0;
 		adder_out <= 0;
-    end
+	end
 end
 
 // Output accumulation result