From: lkcl <lkcl@web>
Date: Sun, 25 Jul 2021 13:20:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~590
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6a97e5299c31d2ea1d000d84646ed10a7f4d91e6;p=libreriscv.git

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diff --git a/conferences/xdc2021.mdwn b/conferences/xdc2021.mdwn
index dafd39846..02d5dbb29 100644
--- a/conferences/xdc2021.mdwn
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@@ -1,3 +1,7 @@
+# Links
+
+* <https://indico.freedesktop.org/event/1/abstracts/32/>
+
 # Abstract
 
 create an entirely Libre Hybrid 3D CPU-VPU-GPU. Critical to that is to have decent Vectorisation support. Most GPUs use predicated SIMD: SIMD has been demonstrated multiple times to be harmful, and with Libre-SOC also needing to run standard CPU workloads as well, designing an ISA and associated compilers and toolcgains was impractical. Therefore a Vector ISA has been designed which, in effect, uses the x86-style "REP" instruction on top of the scalar Power ISA v3.0.