From: Adam Nemet Date: Thu, 3 Apr 2008 19:31:28 +0000 (+0000) Subject: mips.md (any_gt, [...]): New code iterators. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ac935c1503763d48c8f461d6fa8349a38513e85;p=gcc.git mips.md (any_gt, [...]): New code iterators. * config/mips/mips.md (any_gt, any_ge, any_lt, any_le): New code iterators. (u): Add attribute values for gt, gtu, ge, geu, lt, ltu, le and leu. (sgt): Merge sgt and sgtu into new expander. (sgt, sgtu): Remove expanders. (*sgt_): Merge *sgt_ and *sgtu_ into new pattern. (*sgt_, *sgtu_): Remove patterns. (*sgt__mips16): Merge *sgt__mips16 and *sgtu__mips16 into new pattern. (*sgt__mips16, *sgtu__mips16): Remove patterns. (sge): Merge sge and sgeu into new expander. (sge, sgeu): Remove expanders. (*sge_): Merge *sge_ and second *sge_ into new pattern. (*sge_, second *sge_): Remove patterns. (slt): Merge slt and sltu into new expander. (slt, sltu): Remove expanders. (*slt_): Merge *slt_ and *sltu_ into new pattern. (*slt_, *sltu_): Remove patterns. (*slt__mips16): Merge *slt__mips16 and *sltu__mips16 into new pattern. (*slt__mips16, *sltu__mips16): Remove patterns. (sle): Merge sle and sleu into new expander. (sle, sleu): Remove expanders. (*sle_): Merge *sle_ and *sleu_ into new pattern. (*sle_, *sleu_): Remove patterns. (*sle__mips16): Merge *sle__mips16 and *sleu__mips16 into new pattern. (*sle__mips16, *sleu__mips16): Remove patterns. testsuite/ * gcc.target/mips/scc-1.c: New test. From-SVN: r133872 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 126309259da..e57b0d3787d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,39 @@ +2008-04-03 Adam Nemet + + * config/mips/mips.md (any_gt, any_ge, any_lt, any_le): New code + iterators. + (u): Add attribute values for gt, gtu, ge, geu, lt, ltu, le and + leu. + (sgt): Merge sgt and sgtu into new expander. + (sgt, sgtu): Remove expanders. + (*sgt_): Merge *sgt_ and *sgtu_ into new + pattern. + (*sgt_, *sgtu_): Remove patterns. + (*sgt__mips16): Merge *sgt__mips16 and + *sgtu__mips16 into new pattern. + (*sgt__mips16, *sgtu__mips16): Remove patterns. + (sge): Merge sge and sgeu into new expander. + (sge, sgeu): Remove expanders. + (*sge_): Merge *sge_ and second *sge_ into + new pattern. + (*sge_, second *sge_): Remove patterns. + (slt): Merge slt and sltu into new expander. + (slt, sltu): Remove expanders. + (*slt_): Merge *slt_ and *sltu_ into new + pattern. + (*slt_, *sltu_): Remove patterns. + (*slt__mips16): Merge *slt__mips16 and + *sltu__mips16 into new pattern. + (*slt__mips16, *sltu__mips16): Remove patterns. + (sle): Merge sle and sleu into new expander. + (sle, sleu): Remove expanders. + (*sle_): Merge *sle_ and *sleu_ into new + pattern. + (*sle_, *sleu_): Remove patterns. + (*sle__mips16): Merge *sle__mips16 and + *sleu__mips16 into new pattern. + (*sle__mips16, *sleu__mips16): Remove patterns. + 2008-04-03 Jan Hubicka PR tree-optimization/35795 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b5c66622c2a..2083cb9ff50 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -610,9 +610,20 @@ ;; by swapping the operands. (define_code_iterator swapped_fcond [ge gt unge ungt]) +;; These code iterators allow the signed and unsigned scc operations to use +;; the same template. +(define_code_iterator any_gt [gt gtu]) +(define_code_iterator any_ge [ge geu]) +(define_code_iterator any_lt [lt ltu]) +(define_code_iterator any_le [le leu]) + ;; expands to an empty string when doing a signed operation and ;; "u" when doing an unsigned operation. -(define_code_attr u [(sign_extend "") (zero_extend "u")]) +(define_code_attr u [(sign_extend "") (zero_extend "u") + (gt "") (gtu "u") + (ge "") (geu "u") + (lt "") (ltu "u") + (le "") (leu "u")]) ;; is like , but the signed form expands to "s" rather than "". (define_code_attr su [(sign_extend "s") (zero_extend "u")]) @@ -5098,174 +5109,69 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_expand "sgt" - [(set (match_operand:SI 0 "register_operand") - (gt:SI (match_dup 1) - (match_dup 2)))] - "" - { if (mips_expand_scc (GT, operands[0])) DONE; else FAIL; }) - -(define_insn "*sgt_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (gt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] - "!TARGET_MIPS16" - "slt\t%0,%z2,%1" - [(set_attr "type" "slt") - (set_attr "mode" "")]) - -(define_insn "*sgt__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t") - (gt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_MIPS16" - "slt\t%2,%1" - [(set_attr "type" "slt") - (set_attr "mode" "")]) - -(define_expand "sge" - [(set (match_operand:SI 0 "register_operand") - (ge:SI (match_dup 1) - (match_dup 2)))] - "" - { if (mips_expand_scc (GE, operands[0])) DONE; else FAIL; }) - -(define_insn "*sge_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ge:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 1)))] - "!TARGET_MIPS16" - "slt\t%0,%.,%1" - [(set_attr "type" "slt") - (set_attr "mode" "")]) - -(define_expand "slt" - [(set (match_operand:SI 0 "register_operand") - (lt:SI (match_dup 1) - (match_dup 2)))] - "" - { if (mips_expand_scc (LT, operands[0])) DONE; else FAIL; }) - -(define_insn "*slt_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (lt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "arith_operand" "dI")))] - "!TARGET_MIPS16" - "slt\t%0,%1,%2" - [(set_attr "type" "slt") - (set_attr "mode" "")]) - -(define_insn "*slt__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t,t") - (lt:GPR (match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "arith_operand" "d,I")))] - "TARGET_MIPS16" - "slt\t%1,%2" - [(set_attr "type" "slt") - (set_attr "mode" "") - (set_attr_alternative "length" - [(const_int 4) - (if_then_else (match_operand 2 "m16_uimm8_1") - (const_int 4) - (const_int 8))])]) - -(define_expand "sle" - [(set (match_operand:SI 0 "register_operand") - (le:SI (match_dup 1) - (match_dup 2)))] - "" - { if (mips_expand_scc (LE, operands[0])) DONE; else FAIL; }) - -(define_insn "*sle_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (le:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sle_operand" "")))] - "!TARGET_MIPS16" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) + 1); - return "slt\t%0,%1,%2"; -} - [(set_attr "type" "slt") - (set_attr "mode" "")]) - -(define_insn "*sle__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t") - (le:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sle_operand" "")))] - "TARGET_MIPS16" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) + 1); - return "slt\t%1,%2"; -} - [(set_attr "type" "slt") - (set_attr "mode" "") - (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1") - (const_int 4) - (const_int 8)))]) - -(define_expand "sgtu" +(define_expand "sgt" [(set (match_operand:SI 0 "register_operand") - (gtu:SI (match_dup 1) - (match_dup 2)))] + (any_gt:SI (match_dup 1) + (match_dup 2)))] "" - { if (mips_expand_scc (GTU, operands[0])) DONE; else FAIL; }) + { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sgtu_" +(define_insn "*sgt_" [(set (match_operand:GPR 0 "register_operand" "=d") - (gtu:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] + (any_gt:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] "!TARGET_MIPS16" - "sltu\t%0,%z2,%1" + "slt\t%0,%z2,%1" [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_insn "*sgtu__mips16" +(define_insn "*sgt__mips16" [(set (match_operand:GPR 0 "register_operand" "=t") - (gtu:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d")))] + (any_gt:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d")))] "TARGET_MIPS16" - "sltu\t%2,%1" + "slt\t%2,%1" [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_expand "sgeu" +(define_expand "sge" [(set (match_operand:SI 0 "register_operand") - (geu:SI (match_dup 1) - (match_dup 2)))] + (any_ge:SI (match_dup 1) + (match_dup 2)))] "" - { if (mips_expand_scc (GEU, operands[0])) DONE; else FAIL; }) + { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sge_" +(define_insn "*sge_" [(set (match_operand:GPR 0 "register_operand" "=d") - (geu:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 1)))] + (any_ge:GPR (match_operand:GPR 1 "register_operand" "d") + (const_int 1)))] "!TARGET_MIPS16" - "sltu\t%0,%.,%1" + "slt\t%0,%.,%1" [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_expand "sltu" +(define_expand "slt" [(set (match_operand:SI 0 "register_operand") - (ltu:SI (match_dup 1) - (match_dup 2)))] + (any_lt:SI (match_dup 1) + (match_dup 2)))] "" - { if (mips_expand_scc (LTU, operands[0])) DONE; else FAIL; }) + { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sltu_" +(define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "=d") - (ltu:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "arith_operand" "dI")))] + (any_lt:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "arith_operand" "dI")))] "!TARGET_MIPS16" - "sltu\t%0,%1,%2" + "slt\t%0,%1,%2" [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_insn "*sltu__mips16" +(define_insn "*slt__mips16" [(set (match_operand:GPR 0 "register_operand" "=t,t") - (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "arith_operand" "d,I")))] + (any_lt:GPR (match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "arith_operand" "d,I")))] "TARGET_MIPS16" - "sltu\t%1,%2" + "slt\t%1,%2" [(set_attr "type" "slt") (set_attr "mode" "") (set_attr_alternative "length" @@ -5274,33 +5180,33 @@ (const_int 4) (const_int 8))])]) -(define_expand "sleu" +(define_expand "sle" [(set (match_operand:SI 0 "register_operand") - (leu:SI (match_dup 1) - (match_dup 2)))] + (any_le:SI (match_dup 1) + (match_dup 2)))] "" - { if (mips_expand_scc (LEU, operands[0])) DONE; else FAIL; }) + { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sleu_" +(define_insn "*sle_" [(set (match_operand:GPR 0 "register_operand" "=d") - (leu:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sleu_operand" "")))] + (any_le:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "sle_operand" "")))] "!TARGET_MIPS16" { operands[2] = GEN_INT (INTVAL (operands[2]) + 1); - return "sltu\t%0,%1,%2"; + return "slt\t%0,%1,%2"; } [(set_attr "type" "slt") (set_attr "mode" "")]) -(define_insn "*sleu__mips16" +(define_insn "*sle__mips16" [(set (match_operand:GPR 0 "register_operand" "=t") - (leu:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sleu_operand" "")))] + (any_le:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "sle_operand" "")))] "TARGET_MIPS16" { operands[2] = GEN_INT (INTVAL (operands[2]) + 1); - return "sltu\t%1,%2"; + return "slt\t%1,%2"; } [(set_attr "type" "slt") (set_attr "mode" "") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 59bc95a8e9e..22d1cecdaa8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2008-04-03 Adam Nemet + + * gcc.target/mips/scc-1.c: New test. + 2008-04-03 Richard Guenther * gcc.dg/tree-ssa/vrp43.c: New testcase. diff --git a/gcc/testsuite/gcc.target/mips/scc-1.c b/gcc/testsuite/gcc.target/mips/scc-1.c new file mode 100644 index 00000000000..443b0bf7d17 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/scc-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O -mips32" } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$5,\$4} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$0,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$0,\$4} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$4,\$5} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$4,23} 1 } } */ + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \ + NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } \ + MIPS16 int s##N##_16 (int a, int b) { return LHS REL RHS; } \ + MIPS16 int u##N##_16 (unsigned a, unsigned b) { return LHS REL RHS; } + +#define TEST_NO16(N, LHS, REL, RHS) \ + NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \ + NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } + +TEST (1, a, >, b); +TEST_NO16 (2, a, >=, 1); +TEST (3, a, <, b); +TEST (4, a, <=, 22);