From: David Shah <dave@ds0.me>
Date: Tue, 2 Apr 2019 18:47:50 +0000 (+0100)
Subject: memory_bram: Consider read enable for address expansion register
X-Git-Tag: yosys-0.9~208^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6acbc016f43b1464e6322b895f16d01ed51eea18;p=yosys.git

memory_bram: Consider read enable for address expansion register

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 85ed1c053..804aa21f9 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -957,6 +957,8 @@ grow_read_ports:;
 					SigSpec addr_ok_q = addr_ok;
 					if ((pi.clocks || pi.make_outreg) && !addr_ok.empty()) {
 						addr_ok_q = module->addWire(NEW_ID);
+						if (!pi.sig_en.empty())
+							addr_ok = module->Mux(NEW_ID, addr_ok_q, addr_ok, pi.sig_en);
 						module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol);
 					}