From: Luke Kenneth Casson Leighton Date: Sat, 4 Apr 2020 16:21:26 +0000 (+0100) Subject: whoops missed brackets X-Git-Tag: convert-csv-opcode-to-binary~2962 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ad52e429bfcc8f815de14109833eb9288bc9c86;p=libreriscv.git whoops missed brackets --- diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 1ee26d7e6..e43f8f2f6 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -375,9 +375,9 @@ X-Form EA <- b + (RB) load_data <- MEM(EA, 8) RT <- (load_data[56:63] || load_data[48:55] - || load_data[40:47 || load_data[32:39] - || load_data[24:31 || load_data[16:23] - || load_data[8:15 || load_data[0:7]) + || load_data[40:47] || load_data[32:39] + || load_data[24:31] || load_data[16:23] + || load_data[8:15] || load_data[0:7]) Special Registers Altered: