From: Gabe Black <gabeblack@google.com>
Date: Wed, 11 Sep 2019 21:44:09 +0000 (-0700)
Subject: x86: Simplify and consolidate the code that assembles an MSI on x86.
X-Git-Tag: v19.0.0.0~450
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ad5f1516e889d30566851e3ffaa7dad0b14b8ff;p=gem5.git

x86: Simplify and consolidate the code that assembles an MSI on x86.

There is no interrupt response message, and so no need for a function
which would construct one. The other functions which construct the
request can be consolidated since the work being done by each is
incremental. The template parameters can be used to support multiple
types and offsets in a single function, and since that function also
doesn't have to do much work, it makes sense to do everything in one
shot.

Change-Id: I41b202a263a697c5ada6817f3ab2a4728281b894
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20826
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
---

diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 429b0f9f6..d2a5dfa1c 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -76,40 +76,17 @@ namespace X86ISA
 
     static const Addr TriggerIntOffset = 0;
 
-    static inline PacketPtr
-    prepIntRequest(const uint8_t id, Addr offset, Addr size)
+    template<class T>
+    PacketPtr
+    buildIntPacket(Addr addr, T payload)
     {
         RequestPtr req = std::make_shared<Request>(
-            x86InterruptAddress(id, offset),
-            size, Request::UNCACHEABLE,
-            Request::intMasterId);
-
+            addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
         PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
         pkt->allocate();
-        return pkt;
-    }
-
-    template<class T>
-    PacketPtr
-    buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
-    {
-        PacketPtr pkt = prepIntRequest(id, offset, size);
         pkt->setRaw<T>(payload);
         return pkt;
     }
-
-    static inline PacketPtr
-    buildIntRequest(const uint8_t id, TriggerIntMessage payload)
-    {
-        return buildIntRequest(id, payload, TriggerIntOffset,
-                sizeof(TriggerIntMessage));
-    }
-
-    static inline PacketPtr
-    buildIntResponse()
-    {
-        panic("buildIntResponse not implemented.\n");
-    }
 }
 
 #endif
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 274873370..052928043 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -115,7 +115,8 @@ class IntMasterPort : public QueuedMasterPort
     sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing)
     {
         for (auto id: apics) {
-            PacketPtr pkt = buildIntRequest(id, message);
+            Addr addr = x86InterruptAddress(id, TriggerIntOffset);
+            PacketPtr pkt = buildIntPacket(addr, message);
             if (timing) {
                 schedTimingReq(pkt, curTick() + latency);
                 // The target handles cleaning up the packet in timing mode.