From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Oct 2020 17:39:58 +0000 (+0100)
Subject: arg CacheRam read output needs delay by 1 cycle
X-Git-Tag: 24jan2021_ls180~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6adca6f1e1932557d9dcca07036b32f1b50e0079;p=soc.git

arg CacheRam read output needs delay by 1 cycle
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index b3d0b76f..5f96e04a 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1073,7 +1073,7 @@ class DCache(Elaboratable):
             wr_sel_m = Signal(ROW_SIZE)
             _d_out   = Signal(WB_DATA_BITS, name="dout_%d" % i)
 
-            way = CacheRam(ROW_BITS, WB_DATA_BITS, True)
+            way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True)
             setattr(m.submodules, "cacheram_%d" % i, way)
 
             comb += way.rd_en.eq(do_read)