From: Dave Airlie Date: Mon, 19 Feb 2018 06:14:40 +0000 (+0000) Subject: radv/tess: drop tcs_in_layout setting completely. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6adf99165c97fb53f37be1c5b6007632838dd49b;p=mesa.git radv/tess: drop tcs_in_layout setting completely. Inline all calcs at shader creation. Reviewed-by: Samuel Pitoiset Signed-off-by: Dave Airlie --- diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 996add72aef..9eeea597fc8 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -65,7 +65,6 @@ struct radv_shader_context { LLVMValueRef tcs_offchip_layout; LLVMValueRef tcs_out_offsets; LLVMValueRef tcs_out_layout; - LLVMValueRef tcs_in_layout; LLVMValueRef oc_lds; LLVMValueRef merged_wave_info; LLVMValueRef tess_factor_offset; @@ -108,6 +107,7 @@ struct radv_shader_context { uint32_t tcs_patch_outputs_read; uint64_t tcs_outputs_read; uint32_t tcs_vertices_per_patch; + uint32_t tcs_num_inputs; }; enum radeon_llvm_calling_convention { @@ -162,7 +162,11 @@ static LLVMValueRef get_tcs_in_patch_stride(struct radv_shader_context *ctx) { assert (ctx->stage == MESA_SHADER_TESS_CTRL); - return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13); + uint32_t input_vertex_size = ctx->tcs_num_inputs * 16; + uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size; + + input_patch_size /= 4; + return LLVMConstInt(ctx->ac.i32, input_patch_size, false); } static LLVMValueRef @@ -462,7 +466,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx, if (previous_stage == MESA_SHADER_VERTEX) user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx); } - user_sgpr_info->sgpr_count += 4; + user_sgpr_info->sgpr_count += 3; break; case MESA_SHADER_TESS_EVAL: user_sgpr_info->sgpr_count += 1; @@ -764,8 +768,6 @@ static void create_function(struct radv_shader_context *ctx, &ctx->tcs_out_offsets); add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_out_layout); - add_arg(&args, ARG_SGPR, ctx->ac.i32, - &ctx->tcs_in_layout); if (needs_view_index) add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.view_index); @@ -789,8 +791,6 @@ static void create_function(struct radv_shader_context *ctx, &ctx->tcs_out_offsets); add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_out_layout); - add_arg(&args, ARG_SGPR, ctx->ac.i32, - &ctx->tcs_in_layout); if (needs_view_index) add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.view_index); @@ -999,7 +999,7 @@ static void create_function(struct radv_shader_context *ctx, case MESA_SHADER_TESS_CTRL: set_vs_specific_input_locs(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx); - set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4); + set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 3); if (ctx->abi.view_index) set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1); break; @@ -1226,7 +1226,8 @@ load_tcs_varyings(struct ac_shader_abi *abi, unsigned param = shader_io_get_unique_index(location); if (load_input) { - stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8); + uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4; + stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false); dw_addr = get_tcs_in_current_patch_offset(ctx); } else { if (!is_patch) { @@ -3019,6 +3020,10 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, ctx.abi.load_patch_vertices_in = load_patch_vertices_in; ctx.abi.store_tcs_outputs = store_tcs_output; ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out; + if (shader_count == 1) + ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs; + else + ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written); } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) { ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode; ctx.abi.load_tess_varyings = load_tes_input; @@ -3092,8 +3097,11 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) { shader_info->tcs.outputs_written = ctx.tess_outputs_written; shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written; + assert(ctx.tess_outputs_written == ctx.shader_info->info.tcs.outputs_written); + assert(ctx.tess_patch_outputs_written == ctx.shader_info->info.tcs.patch_outputs_written); } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) { shader_info->vs.outputs_written = ctx.tess_outputs_written; + assert(ctx.tess_outputs_written == ctx.shader_info->info.vs.ls_outputs_written); } } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 6d175169343..557d5ec58b3 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -62,7 +62,6 @@ struct radv_blend_state { struct radv_tessellation_state { uint32_t ls_hs_config; - uint32_t tcs_in_layout; uint32_t tcs_out_layout; uint32_t tcs_out_offsets; uint32_t offchip_layout; @@ -1383,8 +1382,6 @@ calculate_tess_state(struct radv_pipeline *pipeline, tess.lds_size = lds_size; - tess.tcs_in_layout = (input_patch_size / 4) | - ((input_vertex_size / 4) << 13); tess.tcs_out_layout = (output_patch_size / 4) | ((output_vertex_size / 4) << 13); tess.tcs_out_offsets = (output_patch0_offset / 16) | @@ -1597,6 +1594,7 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys, if (nir[MESA_SHADER_TESS_CTRL]) { keys[MESA_SHADER_VERTEX].vs.as_ls = true; + keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0; keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices; keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode; @@ -1811,6 +1809,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline, for (int i = 0; i < MESA_SHADER_STAGES; ++i) { if(modules[i] && !pipeline->shaders[i]) { + if (i == MESA_SHADER_TESS_CTRL) { + keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written); + } pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1, pipeline->layout, keys + i, &codes[i], @@ -2614,13 +2615,12 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT); if (loc->sgpr_idx != -1) { uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL]; - assert(loc->num_sgprs == 4); + assert(loc->num_sgprs == 3); assert(!loc->indirect); - radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4); + radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 3); radeon_emit(cs, tess->offchip_layout); radeon_emit(cs, tess->tcs_out_offsets); radeon_emit(cs, tess->tcs_out_layout); - radeon_emit(cs, tess->tcs_in_layout); } loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index ae818280250..1e006622edc 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -69,6 +69,7 @@ struct radv_tcs_variant_key { struct radv_vs_variant_key vs_key; unsigned primitive_mode; unsigned input_vertices; + unsigned num_inputs; uint32_t tes_reads_tess_factors:1; };