From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 19:49:07 +0000 (+0100)
Subject: add TAR and comment BranchInputData fields
X-Git-Tag: div_pipeline~1167
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6afd10d32fb69f36092c411d8e06d5978bee1704;p=soc.git

add TAR and comment BranchInputData fields
---

diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index cab43cf6..6d97102c 100644
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -22,10 +22,11 @@ class BranchInputData(IntegerData):
         # We need both lr and spr for bclr and bcctrl. Bclr can read
         # from both ctr and lr, and bcctrl can write to both ctr and
         # lr.
-        self.lr = Signal(64, reset_less=True)
-        self.spr = Signal(64, reset_less=True)
-        self.cr = Signal(32, reset_less=True)
-        self.cia = Signal(64, reset_less=True)
+        self.lr = Signal(64, reset_less=True)  # Link Register
+        self.spr = Signal(64, reset_less=True) # CTR
+        self.cr = Signal(32, reset_less=True)  # Condition Register(s) CR0-7
+        self.cia = Signal(64, reset_less=True) # Current Instruction Address
+        self.tar = Signal(64, reset_less=True) # Target Address Register
 
     def __iter__(self):
         yield from super().__iter__()
@@ -33,10 +34,11 @@ class BranchInputData(IntegerData):
         yield self.spr
         yield self.cr
         yield self.cia
+        yield self.tar
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.lr.eq(i.lr), self.spr.eq(i.spr),
+        return lst + [self.lr.eq(i.lr), self.spr.eq(i.spr), self.tar.eq(i.tar),
                       self.cr.eq(i.cr), self.cia.eq(i.cia)]