From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 15:27:26 +0000 (+0100) Subject: add cross-reference to bugtracker and wiki X-Git-Tag: div_pipeline~1030 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b02b3a99703f7f04739697e941c294a9b9c9cc1;p=soc.git add cross-reference to bugtracker and wiki --- diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index 996099f9..b8f3f396 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -1,5 +1,10 @@ # Proof of correctness for partitioned equal signal combiner # Copyright (C) 2020 Michael Nolan +""" +Links: + * https://bugs.libre-soc.org/show_bug.cgi?id=331 + * https://libre-soc.org/openpower/isa/fixedlogical/ +""" from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed)