From: Florent Kermarrec Date: Mon, 2 Mar 2015 09:59:43 +0000 (+0100) Subject: sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending... X-Git-Tag: 24jan2021_ls180~2534 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b24562eeaa67ba4f1f082ed3f8a4c99d9a0cf53;p=litex.git sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) --- diff --git a/misoclib/mem/sdram/bus/lasmibus.py b/misoclib/mem/sdram/bus/lasmibus.py index 29aa3e98..7578d0ec 100644 --- a/misoclib/mem/sdram/bus/lasmibus.py +++ b/misoclib/mem/sdram/bus/lasmibus.py @@ -18,7 +18,8 @@ class Interface(Record): ("we", 1, DIR_M_TO_S), ("stb", 1, DIR_M_TO_S), ("req_ack", 1, DIR_S_TO_M), - ("dat_ack", 1, DIR_S_TO_M), + ("dat_w_ack", 1, DIR_S_TO_M), + ("dat_r_ack", 1, DIR_S_TO_M), ("lock", 1, DIR_S_TO_M) ] if nbanks > 1: diff --git a/misoclib/mem/sdram/frontend/dma_lasmi.py b/misoclib/mem/sdram/frontend/dma_lasmi.py index 38da442b..c027b2c1 100644 --- a/misoclib/mem/sdram/frontend/dma_lasmi.py +++ b/misoclib/mem/sdram/frontend/dma_lasmi.py @@ -42,20 +42,13 @@ class Reader(Module): request_enable.eq(rsv_level != fifo_depth) ] - # data available - data_available = lasmim.dat_ack - for i in range(lasmim.read_latency): - new_data_available = Signal() - self.sync += new_data_available.eq(data_available) - data_available = new_data_available - # FIFO fifo = SyncFIFO(lasmim.dw, fifo_depth) self.submodules += fifo self.comb += [ fifo.din.eq(lasmim.dat_r), - fifo.we.eq(data_available), + fifo.we.eq(lasmim.dat_r_ack), self.data.stb.eq(fifo.readable), fifo.re.eq(self.data.ack), @@ -86,15 +79,9 @@ class Writer(Module): fifo.din.eq(self.address_data.d) ] - data_valid = lasmim.dat_ack - for i in range(lasmim.write_latency): - new_data_valid = Signal() - self.sync += new_data_valid.eq(data_valid), - data_valid = new_data_valid - self.comb += [ - fifo.re.eq(data_valid), - If(data_valid, + If(lasmim.dat_w_ack, + fifo.re.eq(1), lasmim.dat_we.eq(2**(lasmim.dw//8)-1), lasmim.dat_w.eq(fifo.dout) ), diff --git a/misoclib/mem/sdram/frontend/wishbone2lasmi.py b/misoclib/mem/sdram/frontend/wishbone2lasmi.py index a2110caf..657c7867 100644 --- a/misoclib/mem/sdram/frontend/wishbone2lasmi.py +++ b/misoclib/mem/sdram/frontend/wishbone2lasmi.py @@ -105,8 +105,6 @@ class WB2LASMI(Module, AutoCSR): fsm = FSM(reset_state="IDLE") self.submodules += fsm - fsm.delayed_enter("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1) - fsm.delayed_enter("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1) fsm.act("IDLE", If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT")) @@ -132,18 +130,17 @@ class WB2LASMI(Module, AutoCSR): fsm.act("EVICT_REQUEST", lasmim.stb.eq(1), lasmim.we.eq(1), - If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK")) - ) - fsm.act("EVICT_WAIT_DATA_ACK", - If(lasmim.dat_ack, NextState("EVICT_DATAD")) + If(lasmim.req_ack, NextState("EVICT_DATA")) ) fsm.act("EVICT_DATA", - write_to_lasmi.eq(1), - word_inc.eq(1), - If(word_is_last(word), - NextState("REFILL_WRTAG"), - ).Else( - NextState("EVICT_REQUEST") + If(lasmim.dat_w_ack, + write_to_lasmi.eq(1), + word_inc.eq(1), + If(word_is_last(word), + NextState("REFILL_WRTAG"), + ).Else( + NextState("EVICT_REQUEST") + ) ) ) @@ -155,17 +152,16 @@ class WB2LASMI(Module, AutoCSR): ) fsm.act("REFILL_REQUEST", lasmim.stb.eq(1), - If(lasmim.req_ack, NextState("REFILL_WAIT_DATA_ACK")) - ) - fsm.act("REFILL_WAIT_DATA_ACK", - If(lasmim.dat_ack, NextState("REFILL_DATAD")) + If(lasmim.req_ack, NextState("REFILL_DATA")) ) fsm.act("REFILL_DATA", - write_from_lasmi.eq(1), - word_inc.eq(1), - If(word_is_last(word), - NextState("TEST_HIT"), - ).Else( - NextState("REFILL_REQUEST") + If(lasmim.dat_r_ack, + write_from_lasmi.eq(1), + word_inc.eq(1), + If(word_is_last(word), + NextState("TEST_HIT"), + ).Else( + NextState("REFILL_REQUEST") + ) ) ) diff --git a/misoclib/mem/sdram/lasmicon/bankmachine.py b/misoclib/mem/sdram/lasmicon/bankmachine.py index 23eb6773..3ee6c083 100644 --- a/misoclib/mem/sdram/lasmicon/bankmachine.py +++ b/misoclib/mem/sdram/lasmicon/bankmachine.py @@ -41,7 +41,7 @@ class BankMachine(Module): self.req_fifo.we.eq(req.stb), req.req_ack.eq(self.req_fifo.writable), - self.req_fifo.re.eq(req.dat_ack), + self.req_fifo.re.eq(req.dat_w_ack | req.dat_r_ack), req.lock.eq(self.req_fifo.readable) ] reqf = self.req_fifo.dout @@ -100,7 +100,8 @@ class BankMachine(Module): If(hit, # NB: write-to-read specification is enforced by multiplexer self.cmd.stb.eq(1), - req.dat_ack.eq(self.cmd.ack), + req.dat_w_ack.eq(self.cmd.ack & reqf.we), + req.dat_r_ack.eq(self.cmd.ack & ~reqf.we), self.cmd.is_read.eq(~reqf.we), self.cmd.is_write.eq(reqf.we), self.cmd.cas_n.eq(0), diff --git a/misoclib/mem/sdram/lasmicon/crossbar.py b/misoclib/mem/sdram/lasmicon/crossbar.py index 18ca51e0..e4414900 100644 --- a/misoclib/mem/sdram/lasmicon/crossbar.py +++ b/misoclib/mem/sdram/lasmicon/crossbar.py @@ -50,7 +50,9 @@ class Crossbar(Module): else: controller_selected = [1]*nmasters master_req_acks = [0]*nmasters - master_dat_acks = [0]*nmasters + master_dat_w_acks = [0]*nmasters + master_dat_r_acks = [0]*nmasters + rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)] self.submodules += rrs for nb, rr in enumerate(rrs): @@ -82,11 +84,28 @@ class Crossbar(Module): ] master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack) for nm, master_req_ack in enumerate(master_req_acks)] - master_dat_acks = [master_dat_ack | ((rr.grant == nm) & bank.dat_ack) - for nm, master_dat_ack in enumerate(master_dat_acks)] + master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack) + for nm, master_dat_w_ack in enumerate(master_dat_w_acks)] + master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack) + for nm, master_dat_r_ack in enumerate(master_dat_r_acks)] + + for nm, master_dat_w_ack in enumerate(master_dat_w_acks): + for i in range(self._write_latency): + new_master_dat_w_ack = Signal() + self.sync += new_master_dat_w_ack.eq(master_dat_w_ack) + master_dat_w_ack = new_master_dat_w_ack + master_dat_w_acks[nm] = master_dat_w_ack + + for nm, master_dat_r_ack in enumerate(master_dat_r_acks): + for i in range(self._read_latency): + new_master_dat_r_ack = Signal() + self.sync += new_master_dat_r_ack.eq(master_dat_r_ack) + master_dat_r_ack = new_master_dat_r_ack + master_dat_r_acks[nm] = master_dat_r_ack self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)] - self.comb += [master.dat_ack.eq(master_dat_ack) for master, master_dat_ack in zip(self._masters, master_dat_acks)] + self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)] + self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)] # route data writes controller_selected_wl = controller_selected