From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Mon, 20 Jul 2015 14:15:18 +0000 (-0500)
Subject: ruby: improved stall and wait debugging
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b52f828cc886cd5d84dfb76a61140869c6add23;p=gem5.git

ruby: improved stall and wait debugging

Added dprintfs and asserts for identifying stall and wait bugs.
---

diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
index d823c0a1f..484d2876b 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -295,7 +295,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
 void
 MessageBuffer::reanalyzeMessages(const Address& addr)
 {
-    DPRINTF(RubyQueue, "ReanalyzeMessages\n");
+    DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
     assert(m_stall_msg_map.count(addr) > 0);
     Tick curTick = m_receiver->clockEdge();
 
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1ac99c882..dfcd61ab2 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -26,8 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
+
+#include "debug/RubyQueue.hh"
+#include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/system/Sequencer.hh"
 #include "mem/ruby/system/System.hh"
 #include "sim/system.hh"
@@ -103,6 +105,9 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
         msgVec->resize(m_in_ports, NULL);
         m_waiting_buffers[addr] = msgVec;
     }
+    DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
+            addr);
+    assert(m_in_ports > m_cur_in_port);
     (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
 }