From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Apr 2020 12:59:03 +0000 (+0000)
Subject: experimenting crushing alu16 experiment7 down while still being routable
X-Git-Tag: partial-core-ls180-gdsii~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b61578ac4df0c46bca2ad0d63ff6e20cf5ad717;p=soclayout.git

experimenting crushing alu16 experiment7 down while still being routable
---

diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py
index 70b6d5e..ebccbf2 100755
--- a/experiments7/doAlu16.py
+++ b/experiments7/doAlu16.py
@@ -97,7 +97,7 @@ class ALU16(Module):
         return matched
 
     def place_datapath(self, datapath_insts, x_orig, y_orig, fold):
-        channel_sff1 = self.to_dbu(60)
+        channel_sff1 = self.to_dbu(0)
         with SessionManager():
             slice_height = self.to_dbu(50.0)
             for i in range(len(datapath_insts)):
@@ -129,7 +129,10 @@ class ALU16(Module):
             if ALU16.match_instance(datapath_insts, 'no2', 'nq', inst): continue
             if ALU16.match_instance(datapath_insts, 'sff1', 'i', inst): continue
 
-        self.place_datapath(datapath_insts, 160.0, 50.0, 1)
+        # place to right of add
+        add, sub = self.submodules
+        add_wid = self.from_dbu(add.ab.getWidth())
+        self.place_datapath(datapath_insts, add_wid, 40.0, 1)
 
     def save(self):
         self.name = self.name + '_r'
@@ -139,7 +142,7 @@ class ALU16(Module):
     def build(self):
 
         h_margin = 0.0
-        v_margin = 50.0
+        v_margin = 40.0
 
         if not self.build_submodules():
             return False
@@ -160,7 +163,7 @@ class ALU16(Module):
             ])) + v_margin
 
             # experiment, over-ride
-            width = 580
+            width = 520
             #width = 1310
             #height = 370
 
@@ -168,9 +171,10 @@ class ALU16(Module):
 
             add_wid = self.from_dbu(add.ab.getWidth())
             sub_ht = self.from_dbu(sub.ab.getHeight())
+            sub_wid = self.from_dbu(sub.ab.getWidth())
 
             self.place_submodule(add, 0, v_margin)
-            self.place_submodule(sub, 400, v_margin)
+            self.place_submodule(sub, width-sub_wid, v_margin)
 
             # TODO: replace with some form of lazy evaluation?
             y_north = self.from_dbu(self.ab.getYMax())
@@ -216,8 +220,8 @@ def scriptMain(editor=None, **kwargs):
         'add', editor,
         east_pins=[
             {'net': 'a({})', 'y': 15.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
-            {'net': 'b({})', 'y': 25.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
-            {'net': 'o({})', 'y': 35.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
+            {'net': 'b({})', 'y': 20.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
+            {'net': 'o({})', 'y': 25.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
         ],
         pads={
             'b({})'.format(BIT_WIDTH-1): (
@@ -231,8 +235,8 @@ def scriptMain(editor=None, **kwargs):
         'sub', editor,
         west_pins=[
             {'net': 'a({})', 'y': 15.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
-            {'net': 'b({})', 'y': 25.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
-            {'net': 'o({})', 'y': 35.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
+            {'net': 'b({})', 'y': 20.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
+            {'net': 'o({})', 'y': 25.0, 'delta': 50.0, 'repeat': BIT_WIDTH, 'layer': 'METAL2'},
         ],
         pads={
             'b({})'.format(BIT_WIDTH-1): (
@@ -241,17 +245,18 @@ def scriptMain(editor=None, **kwargs):
         },
         orientation=Transformation.Orientation.ID,
     )
-    sub.set_ab(180.0, 800.0)
+    sub.set_ab(165.0, 800.0)
 
+    o = 00.0
     alu16 = ALU16(
         'alu16', editor, submodules=[add, sub],
         north_pins=[
-            {'net': 'o({})', 'x': 365.0, 'delta': -5.0, 'repeat': BIT_WIDTH},
+            {'net': 'o({})', 'x': 355.0+o, 'delta': -5.0, 'repeat': BIT_WIDTH},
             {'net': 'op'},
         ],
         south_pins=[
-            {'net': 'a({})', 'x': 205.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
-            {'net': 'b({})', 'x': 295.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
+            {'net': 'a({})', 'x': 205.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
+            {'net': 'b({})', 'x': 210.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
         ],
         west_pins=[
             {'net': 'rst', 'y': 10.0, 'layer': 'METAL2'},
diff --git a/experiments7/utils.py b/experiments7/utils.py
index e575bd3..47d29e7 100644
--- a/experiments7/utils.py
+++ b/experiments7/utils.py
@@ -191,7 +191,7 @@ class Module(object):
         katana.loadGlobalRouting(Anabatic.EngineLoadGrByNet)
         katana.layerAssign(Anabatic.EngineNoNetLayerAssign)
         katana.runNegociate(Katana.Flags.NoFlags)
-        Breakpoint.stop(0, 'After routing {0}'.format(self.cell))
+        #Breakpoint.stop(0, 'After routing {0}'.format(self.cell))
         katana.finalizeLayout()
         result = katana.isDetailedRoutingSuccess()
         katana.destroy()