From: Jean-François Nguyen Date: Sun, 29 Sep 2019 22:12:17 +0000 (+0200) Subject: rpc: add public Records as module ports. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b63c60f86d5ba26766b8c01d32b207cb19251ac;p=nmigen.git rpc: add public Records as module ports. --- diff --git a/nmigen/rpc.py b/nmigen/rpc.py index ac19395..a03ec23 100644 --- a/nmigen/rpc.py +++ b/nmigen/rpc.py @@ -3,7 +3,7 @@ import json import argparse import importlib -from .hdl import Signal, Elaboratable +from .hdl import Signal, Record, Elaboratable from .back import rtlil @@ -68,13 +68,12 @@ def _serve_yosys(modules): try: elaboratable = modules[module_name](*args, **kwargs) - def has_port(elaboratable, port_name): - # By convention, any public attribute that is a Signal is considered a port. - return (not port_name.startswith("_") and - isinstance(getattr(elaboratable, port_name), Signal)) - ports = [getattr(elaboratable, port_name) - for port_name in dir(elaboratable) - if has_port(elaboratable, port_name)] + ports = [] + # By convention, any public attribute that is a Signal or a Record is + # considered a port. + for port_name, port in vars(elaboratable).items(): + if not port_name.startswith("_") and isinstance(port, (Signal, Record)): + ports += port._lhs_signals() rtlil_text = rtlil.convert(elaboratable, name=module_name, ports=ports) response = {"frontend": "ilang", "source": rtlil_text} except Exception as error: