From: lkcl <lkcl@web>
Date: Wed, 19 Apr 2023 17:12:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b6dcd1951321f3b2c086a5eefbf9194891baddf;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn
index c55b934ab..39a0d81fe 100644
--- a/openpower/sv/rfc/ls013.mdwn
+++ b/openpower/sv/rfc/ls013.mdwn
@@ -64,10 +64,12 @@ TODO
 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to
    work with, for best effectiveness.  With no SFFS minimum/maximum instructions
    Simple-V min/max Parallel Reduction is severely compromised.
-2. if you implement any of the FP min/max modes, the rest are not much more
+2. Once one FP min/max mode is implemented the rest are not much more
    hardware.
-3.  SVP64/VSX may have different meaning from SVP64/SFFS,
-    so it is *really* crucial to have SFFS ops even if "equivalent" to VSX.
+3.  There exists similar instructions in VSX. This is frequently used to justify not
+   adding them. However SVP64/VSX may have different meaning from SVP64/SFFS,
+    so it is *really* crucial to have SFFS ops even if "equivalent" to VSX
+   in order for SVP64 to not be compromised (non-orthogonal).
 4. FP min/max are rather complex to implement in software, the most commonly
     used FP max function `fmax` from glibc compiled for SFFS is 32 (!)
     instructions.
@@ -87,6 +89,9 @@ Add the following entries to:
 
 # Floating-Point Instructions
 
+This group is to provide Floating-Point min/max however with IEEE754 having advanced
+to 2019 there are now subtle differences. These are selectable with a Mode Field, `FMM`.
+
 ## `FMM` -- Floating Min/Max Mode
 
 <a id="fmm-floating-min-max-mode"></a>