From: Nick Clifton Date: Wed, 5 May 2004 14:33:14 +0000 (+0000) Subject: Add support for 521x,5249,547x,548x. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b6e92f432c86611c81a5da6880946bad25b59dc;p=binutils-gdb.git Add support for 521x,5249,547x,548x. --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index e22588861f9..5ffb9fea845 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,9 @@ +2004-05-05 Peter Barada + + * bfd_archures.c(bfd_architecture): Add 521x,5249,547x,548x. + * cpu-m68k.c(bfd_m68k_arch): Likewise. + * bfd-in2.h(bfd_architecture): Regenerate. + 2004-05-03 Alan Modra * elf.c (_bfd_elf_rela_local_sym): Set kept_section for excluded diff --git a/bfd/archures.c b/bfd/archures.c index 027ac6a8a45..c66987fe847 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -86,6 +86,10 @@ DESCRIPTION .#define bfd_mach_mcf5407 12 .#define bfd_mach_mcf528x 13 .#define bfd_mach_mcfv4e 14 +.#define bfd_mach_mcf521x 15 +.#define bfd_mach_mcf5249 16 +.#define bfd_mach_mcf547x 17 +.#define bfd_mach_mcf548x 18 . bfd_arch_vax, {* DEC Vax *} . bfd_arch_i960, {* Intel 960 *} . {* The order of the following is important. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index c2463566968..ee194f986c6 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1505,6 +1505,10 @@ enum bfd_architecture #define bfd_mach_mcf5407 12 #define bfd_mach_mcf528x 13 #define bfd_mach_mcfv4e 14 +#define bfd_mach_mcf521x 15 +#define bfd_mach_mcf5249 16 +#define bfd_mach_mcf547x 17 +#define bfd_mach_mcf548x 18 bfd_arch_vax, /* DEC Vax */ bfd_arch_i960, /* Intel 960 */ /* The order of the following is important. diff --git a/bfd/cpu-m68k.c b/bfd/cpu-m68k.c index 426f583dec3..c4112d3f589 100644 --- a/bfd/cpu-m68k.c +++ b/bfd/cpu-m68k.c @@ -41,7 +41,11 @@ static const bfd_arch_info_type arch_info_struct[] = N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]), N(bfd_mach_m68060, "m68k:68060", FALSE, &arch_info_struct[12]), N(bfd_mach_mcf528x, "m68k:528x", FALSE, &arch_info_struct[13]), - N(bfd_mach_mcfv4e, "m68k:cfv4e", FALSE, 0), + N(bfd_mach_mcf521x, "m68k:521x", FALSE, &arch_info_struct[14]), + N(bfd_mach_mcf5249, "m68k:5249", FALSE, &arch_info_struct[15]), + N(bfd_mach_mcf547x, "m68k:547x", FALSE, &arch_info_struct[16]), + N(bfd_mach_mcf548x, "m68k:548x", FALSE, &arch_info_struct[17]), + N(bfd_mach_mcfv4e, "m68k:cfv4e", FALSE, 0), }; const bfd_arch_info_type bfd_m68k_arch = diff --git a/gas/ChangeLog b/gas/ChangeLog index f1a6ee1e77a..f9227da54d9 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2004-05-05 Peter Barada + + * config/tc-m68k.c: Add find_cf_chip to print list of valid + chips for invalid coldfire instructions, rename selectors + for ColdFire sub-variants, add 521x,5249,547x,548x and aliases, + add current_chip to track which chip is referred to(including save/restore), + use current_chip to select control registers, not current_arch. + (md_show_usage): Add new chips. + * doc/c-m68k.texi: Document new command line switches. + 2004-05-05 Jakub Jelinek * tc-s390.h (md_do_align, HANDLE_ALIGN): Remove. diff --git a/gas/NEWS b/gas/NEWS index 6391874cfb3..74b7ae72173 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Support for Motorola MCF521x/5249/547x/548x added. + * Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC instrucitons. diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 86fa9dc7a81..89c2df9c298 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -235,14 +235,14 @@ struct m68k_it reloc[5]; /* Five is enough??? */ }; -#define cpu_of_arch(x) ((x) & (m68000up | mcf)) +#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a)) #define float_of_arch(x) ((x) & mfloat) #define mmu_of_arch(x) ((x) & mmmu) -#define arch_coldfire_p(x) ((x) & mcf) -#define arch_coldfire_v4e_p(x) ((x) & mcfv4e) +#define arch_coldfire_p(x) ((x) & mcfisa_a) +#define arch_coldfire_fpu(x) ((x) & cfloat) /* Macros for determining if cpu supports a specific addressing mode. */ -#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e)) +#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b)) static struct m68k_it the_ins; /* The instruction being assembled. */ @@ -361,62 +361,85 @@ static void s_mri_endw PARAMS ((int)); static void md_convert_frag_1 PARAMS ((fragS *)); static int current_architecture; +static int current_chip; struct m68k_cpu { unsigned long arch; + unsigned long chip; const char *name; int alias; }; static const struct m68k_cpu archs[] = { - { m68000, "68000", 0 }, - { m68010, "68010", 0 }, - { m68020, "68020", 0 }, - { m68030, "68030", 0 }, - { m68040, "68040", 0 }, - { m68060, "68060", 0 }, - { cpu32, "cpu32", 0 }, - { m68881, "68881", 0 }, - { m68851, "68851", 0 }, - { mcf5200, "5200", 0 }, - { mcf5206e, "5206e", 0 }, - { mcf528x|mcfmac, "528x", 0 }, - { mcf5307|mcfmac, "5307", 0 }, - { mcf5407|mcfmac, "5407", 0 }, - { mcfv4e|mcfemac, "cfv4e", 0 }, + { m68000, m68000, "68000", 0 }, + { m68010, m68010, "68010", 0 }, + { m68020, m68020, "68020", 0 }, + { m68030, m68030, "68030", 0 }, + { m68040, m68040, "68040", 0 }, + { m68060, m68060, "68060", 0 }, + { cpu32, cpu32, "cpu32", 0 }, + { m68881, m68881, "68881", 0 }, + { m68851, m68851, "68851", 0 }, + { mcfisa_a, mcf5200, "5200", 0 }, + { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 }, + { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 }, + { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 }, /* Aliases (effectively, so far as gas is concerned) for the above cpus. */ - { m68020, "68k", 1 }, - { m68000, "68008", 1 }, - { m68000, "68302", 1 }, - { m68000, "68306", 1 }, - { m68000, "68307", 1 }, - { m68000, "68322", 1 }, - { m68000, "68356", 1 }, - { m68000, "68ec000", 1 }, - { m68000, "68hc000", 1 }, - { m68000, "68hc001", 1 }, - { m68020, "68ec020", 1 }, - { m68030, "68ec030", 1 }, - { m68040, "68ec040", 1 }, - { m68060, "68ec060", 1 }, - { cpu32, "68330", 1 }, - { cpu32, "68331", 1 }, - { cpu32, "68332", 1 }, - { cpu32, "68333", 1 }, - { cpu32, "68334", 1 }, - { cpu32, "68336", 1 }, - { cpu32, "68340", 1 }, - { cpu32, "68341", 1 }, - { cpu32, "68349", 1 }, - { cpu32, "68360", 1 }, - { m68881, "68882", 1 }, - { mcf5200, "5202", 1 }, - { mcf5200, "5204", 1 }, - { mcf5200, "5206", 1 }, - { mcf5407|mcfmac, "cfv4", 1 }, + { m68020, m68020, "68k", 1 }, + { m68000, m68000, "68008", 1 }, + { m68000, m68000, "68302", 1 }, + { m68000, m68000, "68306", 1 }, + { m68000, m68000, "68307", 1 }, + { m68000, m68000, "68322", 1 }, + { m68000, m68000, "68356", 1 }, + { m68000, m68000, "68ec000", 1 }, + { m68000, m68000, "68hc000", 1 }, + { m68000, m68000, "68hc001", 1 }, + { m68020, m68020, "68ec020", 1 }, + { m68030, m68030, "68ec030", 1 }, + { m68040, m68040, "68ec040", 1 }, + { m68060, m68060, "68ec060", 1 }, + { cpu32, cpu32, "68330", 1 }, + { cpu32, cpu32, "68331", 1 }, + { cpu32, cpu32, "68332", 1 }, + { cpu32, cpu32, "68333", 1 }, + { cpu32, cpu32, "68334", 1 }, + { cpu32, cpu32, "68336", 1 }, + { cpu32, cpu32, "68340", 1 }, + { cpu32, cpu32, "68341", 1 }, + { cpu32, cpu32, "68349", 1 }, + { cpu32, cpu32, "68360", 1 }, + { m68881, m68881, "68882", 1 }, + { mcfisa_a, mcf5200, "5202", 1 }, + { mcfisa_a, mcf5200, "5204", 1 }, + { mcfisa_a, mcf5200, "5206", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 }, }; static const int n_archs = sizeof (archs) / sizeof (archs[0]); @@ -660,12 +683,80 @@ static char alt_notend_table[256]; || (*s == ':' \ && alt_notend_table[(unsigned char) s[1]]))) +/* Return a human readable string holding the list of chips that are + valid for a particular architecture, suppressing aliases (unless + there is only one of them). */ + +static char * +find_cf_chip (int architecture) +{ + static char buf[1024]; + int i, j, n_chips, n_alias; + char *cp; + + strcpy (buf, " ("); + cp = buf + strlen (buf); + + for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i) + if (archs[i].arch & architecture) + { + n_chips++; + if (archs[i].alias) + n_alias++; + } + + if (n_chips == 0) + as_fatal (_("no matching ColdFire architectures found")); + + if (n_alias > 1) + n_chips -= n_alias; + + for (i = 0, j = 0; i < n_archs && j < n_chips; ++i) + if (archs[i].arch & architecture) + { + if (j) + { + if (((j == n_chips - 1) && !(n_alias > 1))|| ! n_alias) + { + if (n_chips == 2) + { + strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + else + { + strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + } + else + { + strncpy (cp, ", ", (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + } + strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + j++; + } + + if (n_alias > 1) + { + strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + + strncpy (cp, ")", (sizeof (buf) - (cp - buf))); + + return buf; +} + #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER) #ifdef NO_PCREL_RELOCS int -make_pcrel_absolute(fixP, add_number) +make_pcrel_absolute (fixP, add_number) fixS *fixP; long *add_number; { @@ -677,14 +768,14 @@ make_pcrel_absolute(fixP, add_number) if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */ { if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative branch to absolute jump")); + as_fatal (_("Tried to convert PC relative branch to absolute jump")); opcode[0] = 0x4e; opcode[1] = 0xf9; } else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */ { if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); + as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); opcode[0] = 0x4e; opcode[1] = 0xb9; } @@ -1925,13 +2016,40 @@ m68k_ip (instring) { char buf[200], *cp; - strcpy (buf, - _("invalid instruction for this architecture; needs ")); + strncpy (buf, + _("invalid instruction for this architecture; needs "), sizeof (buf)); cp = buf + strlen (buf); switch (ok_arch) { + case mcfisa_a: + strncpy (cp, _("ColdFire ISA_A"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfhwdiv: + strncpy (cp, _("ColdFire hardware divide"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfisa_aa: + strncpy (cp, _("ColdFire ISA_A+"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfisa_b: + strncpy (cp, _("ColdFire ISA_B"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; case cfloat: - strcpy (cp, _("ColdFire fpu (cfv4e)")); + strncpy (cp, _("ColdFire fpu"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); break; case mfloat: strcpy (cp, _("fpu (68040, 68060 or 68881/68882)")); @@ -1951,9 +2069,8 @@ m68k_ip (instring) default: { int got_one = 0, idx; - for (idx = 0; - idx < (int) (sizeof (archs) / sizeof (archs[0])); - idx++) + + for (idx = 0; idx < n_archs; idx++) { if ((archs[idx].arch & ok_arch) && ! archs[idx].alias) @@ -2281,7 +2398,7 @@ m68k_ip (instring) && cpu_of_arch (current_architecture) < m68020) || (opP->index.scale == 8 && (arch_coldfire_p (current_architecture) - && !arch_coldfire_v4e_p(current_architecture)))) + && !arch_coldfire_fpu (current_architecture)))) { opP->error = _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); @@ -3377,7 +3494,7 @@ install_operand (mode, val) default: as_fatal (_("failed sanity check.")); } -} /* install_operand() */ +} static void install_gen_operand (mode, val) @@ -3411,12 +3528,10 @@ install_gen_operand (mode, val) default: as_fatal (_("failed sanity check.")); } -} /* install_gen_operand() */ +} -/* - * verify that we have some number of paren pairs, do m68k_ip_op(), and - * then deal with the bitfield hack. - */ +/* Verify that we have some number of paren pairs, do m68k_ip_op(), and + then deal with the bitfield hack. */ static char * crack_operand (str, opP) @@ -4185,10 +4300,11 @@ static void select_control_regs () { /* Note which set of "movec" control registers is available. */ - switch (cpu_of_arch (current_architecture)) + switch (current_chip) { case 0: - as_warn (_("architecture not yet selected: defaulting to 68020")); + if (verbose) + as_warn (_("architecture not yet selected: defaulting to 68020")); control_regs = m68020_control_regs; break; @@ -4218,9 +4334,11 @@ select_control_regs () control_regs = mcf_control_regs; break; case mcf528x: + case mcf521x: control_regs = mcf528x_control_regs; break; - case mcfv4e: + case mcf5470: + case mcf5480: control_regs = mcfv4e_control_regs; break; default: @@ -4628,7 +4746,7 @@ md_convert_frag_1 (fragP) if (fragP->fr_opcode[0] == 0x61) /* jbsr */ { if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); + as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, @@ -4638,7 +4756,7 @@ md_convert_frag_1 (fragP) else if (fragP->fr_opcode[0] == 0x60) /* jbra */ { if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative branch to absolute jump")); + as_fatal (_("Tried to convert PC relative branch to absolute jump")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, @@ -4654,7 +4772,7 @@ md_convert_frag_1 (fragP) break; case TAB (BRABSJCOND, LONG): if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); /* Only Bcc 68000 instructions can come here Change bcc into b!cc/jmp absl long. */ @@ -4694,7 +4812,7 @@ md_convert_frag_1 (fragP) Change dbcc into dbcc/bral. JF: these used to be fr_opcode[2-7], but that's wrong. */ if (flag_keep_pcrel) - as_fatal(_("Tried to convert DBcc to absolute jump")); + as_fatal (_("Tried to convert DBcc to absolute jump")); *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; @@ -4713,7 +4831,7 @@ md_convert_frag_1 (fragP) Change dbcc into dbcc/jmp. JF: these used to be fr_opcode[2-7], but that's wrong. */ if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; @@ -4777,7 +4895,7 @@ md_convert_frag_1 (fragP) break; case TAB (ABSTOPCREL, LONG): if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); /* The thing to do here is force it to ABSOLUTE LONG, since ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) @@ -5037,10 +5155,10 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) { valueT offset; - if (!HAVE_LONG_BRANCH(current_architecture)) + if (!HAVE_LONG_BRANCH (current_architecture)) { if (flag_keep_pcrel) - as_fatal(_("Tried to convert PC relative branch to absolute jump")); + as_fatal (_("Tried to convert PC relative branch to absolute jump")); offset = to_addr - S_GET_VALUE (to_symbol); md_number_to_chars (ptr, (valueT) 0x4EF9, 2); md_number_to_chars (ptr + 2, (valueT) offset, 4); @@ -5306,6 +5424,7 @@ mri_chip () else current_architecture &= m68881 | m68851; current_architecture |= archs[i].arch; + current_chip |= archs[i].chip; while (*input_line_pointer == '/') { @@ -5684,6 +5803,7 @@ struct save_opts int keep_locals; int short_refs; int architecture; + int chip; int quick; int rel32; int listing; @@ -5709,6 +5829,7 @@ s_save (ignore) s->keep_locals = flag_keep_locals; s->short_refs = flag_short_refs; s->architecture = current_architecture; + s->chip = current_chip; s->quick = m68k_quick; s->rel32 = m68k_rel32; s->listing = listing; @@ -5743,6 +5864,7 @@ s_restore (ignore) flag_keep_locals = s->keep_locals; flag_short_refs = s->short_refs; current_architecture = s->architecture; + current_chip = s->chip; m68k_quick = s->quick; m68k_rel32 = s->rel32; listing = s->listing; @@ -7095,6 +7217,7 @@ md_parse_option (c, arg) { current_architecture &= ~m68000up; current_architecture |= arch; + current_chip |= archs[i].chip; } else if (arch == m68881) { @@ -7212,8 +7335,8 @@ md_show_usage (stream) -l use 1 word for refs to undefined symbols [default 2]\n\ -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\ -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\ --m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m528x | -m5307 |\n\ --m5407 | -mcfv4 | -mcfv4e\n\ +-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\ +-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\ specify variant of 680X0 architecture [default %s]\n\ -m68881 | -m68882 | -mno-68881 | -mno-68882\n\ target has/lacks floating-point coprocessor\n\ diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi index cafad4d59e6..965693f970b 100644 --- a/gas/doc/c-m68k.texi +++ b/gas/doc/c-m68k.texi @@ -1,4 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003 +@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, 2004 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -169,9 +169,13 @@ Assemble for the CPU32 family of chips. @item -m5204 @item -m5206 @item -m5206e +@item -m521x +@item -m5249 @item -m528x @item -m5307 @item -m5407 +@item -m547x +@item -m548x @item -mcfv4 @item -mcfv4e Assemble for the ColdFire family of chips. diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 7cc70635093..9d7ab06db5b 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,4 +1,8 @@ -2004-04-22 Peter Barada +2004-05-05 Peter Barada + + * m68k.h: Switch from ColdFire chip name to core variant. + +2004-04-22 Peter Barada * m68k.h: Add mcfmac/mcfemac definitions. Update operand descriptions for new EMAC cases. diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h index baa766c1650..daef737d572 100644 --- a/include/opcode/m68k.h +++ b/include/opcode/m68k.h @@ -35,15 +35,27 @@ #define m68881 0x040 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ #define m68851 0x080 -#define cpu32 0x100 /* e.g., 68332 */ -#define mcf5200 0x200 -#define mcf5206e 0x400 -#define mcf5307 0x800 -#define mcf5407 0x1000 -#define mcfv4e 0x2000 -#define mcf528x 0x4000 -#define mcfmac 0x8000 -#define mcfemac 0x10000 +#define cpu32 0x100 /* e.g., 68332 */ + +#define mcfmac 0x200 /* ColdFire MAC. */ +#define mcfemac 0x400 /* ColdFire EMAC. */ +#define cfloat 0x800 /* ColdFire FPU. */ +#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ + +#define mcfisa_a 0x2000 /* ColdFire ISA_A. */ +#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ +#define mcfisa_b 0x8000 /* ColdFire ISA_B. */ +#define mcfusp 0x10000 /* ColdFire USP instructions. */ + +#define mcf5200 0x20000 +#define mcf5206e 0x40000 +#define mcf521x 0x80000 +#define mcf5249 0x100000 +#define mcf528x 0x200000 +#define mcf5307 0x400000 +#define mcf5407 0x800000 +#define mcf5470 0x1000000 +#define mcf5480 0x2000000 /* Handy aliases. */ #define m68040up (m68040 | m68060) @@ -51,13 +63,7 @@ #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) -#define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) -#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) -#define mcf5307up (mcf5307 | mcf5407 | mcfv4e) -#define mcfv4up (mcf5407 | mcfv4e) -#define mcfv4eup (mcfv4e) -#define cfloat (mcfv4e) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c15b19b5434..aba0460dff6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2004-05-05 Peter Barada + + * m68k-dis.c(print_insn_m68k): Add new chips, use core + variants in arch_mask. Only set m68881/68851 for 68k chips. + * m68k-op.c: Switch from ColdFire chips to core variants. + 2004-05-05 Alan Modra PR 146. diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c index 365d54aafa4..e27a9a678f9 100644 --- a/opcodes/m68k-dis.c +++ b/opcodes/m68k-dis.c @@ -240,48 +240,52 @@ print_insn_m68k (memaddr, info) arch_mask = (unsigned int) -1; break; case bfd_mach_m68000: - arch_mask = m68000; + arch_mask = m68000|m68881|m68851; break; case bfd_mach_m68008: - arch_mask = m68008; + arch_mask = m68008|m68881|m68851; break; case bfd_mach_m68010: - arch_mask = m68010; + arch_mask = m68010|m68881|m68851; break; case bfd_mach_m68020: - arch_mask = m68020; + arch_mask = m68020|m68881|m68851; break; case bfd_mach_m68030: - arch_mask = m68030; + arch_mask = m68030|m68881|m68851; break; case bfd_mach_m68040: - arch_mask = m68040; + arch_mask = m68040|m68881|m68851; break; case bfd_mach_m68060: - arch_mask = m68060; + arch_mask = m68060|m68881|m68851; break; case bfd_mach_mcf5200: - arch_mask = mcf5200; + arch_mask = mcfisa_a; break; + case bfd_mach_mcf521x: case bfd_mach_mcf528x: - arch_mask = mcf528x | mcfmac; + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; break; case bfd_mach_mcf5206e: - arch_mask = mcf5206e | mcfmac; + arch_mask = mcfisa_a|mcfhwdiv|mcfmac; + break; + case bfd_mach_mcf5249: + arch_mask = mcfisa_a|mcfhwdiv|mcfemac; break; case bfd_mach_mcf5307: - arch_mask = mcf5307 | mcfmac; + arch_mask = mcfisa_a|mcfhwdiv|mcfmac; break; case bfd_mach_mcf5407: - arch_mask = mcf5407 | mcfmac; + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; break; + case bfd_mach_mcf547x: + case bfd_mach_mcf548x: case bfd_mach_mcfv4e: - arch_mask = mcfv4e | mcfemac; + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; break; } - arch_mask |= m68881 | m68851; - bestmask = 0; FETCH_DATA (info, buffer + 2); major_opcode = (buffer[0] >> 4) & 15; diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c index 805a0fbc626..9e2e77eaa9a 100644 --- a/opcodes/m68k-opc.c +++ b/opcodes/m68k-opc.c @@ -36,16 +36,16 @@ const struct m68k_opcode m68k_opcodes[] = {"abcd", one(0140410), one(0170770), "-s-d", m68000up }, {"addaw", one(0150300), one(0170700), "*wAd", m68000up }, -{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcf }, +{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"addib", one(0003000), one(0177700), "#b$s", m68000up }, {"addiw", one(0003100), one(0177700), "#w$s", m68000up }, {"addil", one(0003200), one(0177700), "#l$s", m68000up }, -{"addil", one(0003200), one(0177700), "#lDs", mcf }, +{"addil", one(0003200), one(0177700), "#lDs", mcfisa_a }, {"addqb", one(0050000), one(0170700), "Qd$b", m68000up }, {"addqw", one(0050100), one(0170700), "Qd%w", m68000up }, -{"addql", one(0050200), one(0170700), "Qd%l", m68000up | mcf }, +{"addql", one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, /* The add opcode can generate the adda, addi, and addq instructions. */ {"addb", one(0050000), one(0170700), "Qd$b", m68000up }, @@ -57,18 +57,18 @@ const struct m68k_opcode m68k_opcodes[] = {"addw", one(0003100), one(0177700), "#w$s", m68000up }, {"addw", one(0150100), one(0170700), "*wDd", m68000up }, {"addw", one(0150500), one(0170700), "Dd~w", m68000up }, -{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcf }, +{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, {"addl", one(0003200), one(0177700), "#l$s", m68000up }, -{"addl", one(0003200), one(0177700), "#lDs", mcf }, -{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcf }, -{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcf }, -{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcf }, +{"addl", one(0003200), one(0177700), "#lDs", mcfisa_a }, +{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, {"addxb", one(0150400), one(0170770), "DsDd", m68000up }, {"addxb", one(0150410), one(0170770), "-s-d", m68000up }, {"addxw", one(0150500), one(0170770), "DsDd", m68000up }, {"addxw", one(0150510), one(0170770), "-s-d", m68000up }, -{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcf }, +{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, {"addxl", one(0150610), one(0170770), "-s-d", m68000up }, {"andib", one(0001000), one(0177700), "#b$s", m68000up }, @@ -76,7 +76,7 @@ const struct m68k_opcode m68k_opcodes[] = {"andiw", one(0001100), one(0177700), "#w$s", m68000up }, {"andiw", one(0001174), one(0177777), "#wSs", m68000up }, {"andil", one(0001200), one(0177700), "#l$s", m68000up }, -{"andil", one(0001200), one(0177700), "#lDs", mcf }, +{"andil", one(0001200), one(0177700), "#lDs", mcfisa_a }, {"andi", one(0001100), one(0177700), "#w$s", m68000up }, {"andi", one(0001074), one(0177777), "#bCs", m68000up }, {"andi", one(0001174), one(0177777), "#wSs", m68000up }, @@ -91,9 +91,9 @@ const struct m68k_opcode m68k_opcodes[] = {"andw", one(0140100), one(0170700), ";wDd", m68000up }, {"andw", one(0140500), one(0170700), "Dd~w", m68000up }, {"andl", one(0001200), one(0177700), "#l$s", m68000up }, -{"andl", one(0001200), one(0177700), "#lDs", mcf }, -{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcf }, -{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcf }, +{"andl", one(0001200), one(0177700), "#lDs", mcfisa_a }, +{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, +{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, {"and", one(0001100), one(0177700), "#w$w", m68000up }, {"and", one(0001074), one(0177777), "#bCs", m68000up }, {"and", one(0001174), one(0177777), "#wSs", m68000up }, @@ -105,84 +105,84 @@ const struct m68k_opcode m68k_opcodes[] = {"aslw", one(0160500), one(0170770), "QdDs", m68000up }, {"aslw", one(0160540), one(0170770), "DdDs", m68000up }, {"aslw", one(0160700), one(0177700), "~s", m68000up }, -{"asll", one(0160600), one(0170770), "QdDs", m68000up | mcf }, -{"asll", one(0160640), one(0170770), "DdDs", m68000up | mcf }, +{"asll", one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"asll", one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, {"asrb", one(0160000), one(0170770), "QdDs", m68000up }, {"asrb", one(0160040), one(0170770), "DdDs", m68000up }, {"asrw", one(0160100), one(0170770), "QdDs", m68000up }, {"asrw", one(0160140), one(0170770), "DdDs", m68000up }, {"asrw", one(0160300), one(0177700), "~s", m68000up }, -{"asrl", one(0160200), one(0170770), "QdDs", m68000up | mcf }, -{"asrl", one(0160240), one(0170770), "DdDs", m68000up | mcf }, - -{"bhiw", one(0061000), one(0177777), "BW", m68000up | mcf }, -{"blsw", one(0061400), one(0177777), "BW", m68000up | mcf }, -{"bccw", one(0062000), one(0177777), "BW", m68000up | mcf }, -{"bcsw", one(0062400), one(0177777), "BW", m68000up | mcf }, -{"bnew", one(0063000), one(0177777), "BW", m68000up | mcf }, -{"beqw", one(0063400), one(0177777), "BW", m68000up | mcf }, -{"bvcw", one(0064000), one(0177777), "BW", m68000up | mcf }, -{"bvsw", one(0064400), one(0177777), "BW", m68000up | mcf }, -{"bplw", one(0065000), one(0177777), "BW", m68000up | mcf }, -{"bmiw", one(0065400), one(0177777), "BW", m68000up | mcf }, -{"bgew", one(0066000), one(0177777), "BW", m68000up | mcf }, -{"bltw", one(0066400), one(0177777), "BW", m68000up | mcf }, -{"bgtw", one(0067000), one(0177777), "BW", m68000up | mcf }, -{"blew", one(0067400), one(0177777), "BW", m68000up | mcf }, - -{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, - -{"bhis", one(0061000), one(0177400), "BB", m68000up | mcf }, -{"blss", one(0061400), one(0177400), "BB", m68000up | mcf }, -{"bccs", one(0062000), one(0177400), "BB", m68000up | mcf }, -{"bcss", one(0062400), one(0177400), "BB", m68000up | mcf }, -{"bnes", one(0063000), one(0177400), "BB", m68000up | mcf }, -{"beqs", one(0063400), one(0177400), "BB", m68000up | mcf }, -{"bvcs", one(0064000), one(0177400), "BB", m68000up | mcf }, -{"bvss", one(0064400), one(0177400), "BB", m68000up | mcf }, -{"bpls", one(0065000), one(0177400), "BB", m68000up | mcf }, -{"bmis", one(0065400), one(0177400), "BB", m68000up | mcf }, -{"bges", one(0066000), one(0177400), "BB", m68000up | mcf }, -{"blts", one(0066400), one(0177400), "BB", m68000up | mcf }, -{"bgts", one(0067000), one(0177400), "BB", m68000up | mcf }, -{"bles", one(0067400), one(0177400), "BB", m68000up | mcf }, - -{"jhi", one(0061000), one(0177400), "Bg", m68000up | mcf }, -{"jls", one(0061400), one(0177400), "Bg", m68000up | mcf }, -{"jcc", one(0062000), one(0177400), "Bg", m68000up | mcf }, -{"jcs", one(0062400), one(0177400), "Bg", m68000up | mcf }, -{"jne", one(0063000), one(0177400), "Bg", m68000up | mcf }, -{"jeq", one(0063400), one(0177400), "Bg", m68000up | mcf }, -{"jvc", one(0064000), one(0177400), "Bg", m68000up | mcf }, -{"jvs", one(0064400), one(0177400), "Bg", m68000up | mcf }, -{"jpl", one(0065000), one(0177400), "Bg", m68000up | mcf }, -{"jmi", one(0065400), one(0177400), "Bg", m68000up | mcf }, -{"jge", one(0066000), one(0177400), "Bg", m68000up | mcf }, -{"jlt", one(0066400), one(0177400), "Bg", m68000up | mcf }, -{"jgt", one(0067000), one(0177400), "Bg", m68000up | mcf }, -{"jle", one(0067400), one(0177400), "Bg", m68000up | mcf }, - -{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcf }, +{"asrl", one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"asrl", one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, + +{"bhiw", one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, +{"blsw", one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bccw", one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bcsw", one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bnew", one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, +{"beqw", one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bvcw", one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bvsw", one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bplw", one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bmiw", one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bgew", one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bltw", one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bgtw", one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, +{"blew", one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, + +{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, + +{"bhis", one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, +{"blss", one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bccs", one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bcss", one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bnes", one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, +{"beqs", one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bvcs", one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bvss", one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bpls", one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bmis", one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bges", one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, +{"blts", one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bgts", one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bles", one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, + +{"jhi", one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jls", one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jcc", one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jcs", one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jne", one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jeq", one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jvc", one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jvs", one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jpl", one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jmi", one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jge", one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jlt", one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jgt", one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jle", one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, + +{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"bchg", one(0004100), one(0177700), "#b$s", m68000up }, -{"bchg", one(0004100), one(0177700), "#bqs", mcf }, +{"bchg", one(0004100), one(0177700), "#bqs", mcfisa_a }, -{"bclr", one(0000600), one(0170700), "Dd$s", m68000up | mcf }, +{"bclr", one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"bclr", one(0004200), one(0177700), "#b$s", m68000up }, -{"bclr", one(0004200), one(0177700), "#bqs", mcf }, +{"bclr", one(0004200), one(0177700), "#bqs", mcfisa_a }, {"bfchg", two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, {"bfclr", two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, @@ -195,28 +195,28 @@ const struct m68k_opcode m68k_opcodes[] = {"bgnd", one(0045372), one(0177777), "", cpu32 }, -{"bitrev", one(0000300), one(0177770), "Ds", mcf528x}, +{"bitrev", one(0000300), one(0177770), "Ds", mcfisa_aa}, {"bkpt", one(0044110), one(0177770), "ts", m68010up }, -{"braw", one(0060000), one(0177777), "BW", m68000up | mcf }, -{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bras", one(0060000), one(0177400), "BB", m68000up | mcf }, +{"braw", one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bras", one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bset", one(0000700), one(0170700), "Dd$s", m68000up | mcf }, -{"bset", one(0000700), one(0170700), "Ddvs", mcf }, +{"bset", one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{"bset", one(0000700), one(0170700), "Ddvs", mcfisa_a }, {"bset", one(0004300), one(0177700), "#b$s", m68000up }, -{"bset", one(0004300), one(0177700), "#bqs", mcf }, +{"bset", one(0004300), one(0177700), "#bqs", mcfisa_a }, -{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcf }, -{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfv4up}, -{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcf }, +{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, +{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, -{"btst", one(0000400), one(0170700), "Dd;b", m68000up | mcf }, +{"btst", one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, {"btst", one(0004000), one(0177700), "#b@s", m68000up }, -{"btst", one(0004000), one(0177700), "#bqs", mcf }, +{"btst", one(0004000), one(0177700), "#bqs", mcfisa_a }, -{"byterev", one(0001300), one(0177770), "Ds", mcf528x}, +{"byterev", one(0001300), one(0177770), "Ds", mcfisa_aa}, {"callm", one(0003300), one(0177700), "#b!s", m68020 }, @@ -245,30 +245,30 @@ const struct m68k_opcode m68k_opcodes[] = {"cinvp", one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, {"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, -{"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcf }, +{"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, {"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, #undef SCOPE_LINE #undef SCOPE_PAGE #undef SCOPE_ALL -{"clrb", one(0041000), one(0177700), "$s", m68000up | mcf }, -{"clrw", one(0041100), one(0177700), "$s", m68000up | mcf }, -{"clrl", one(0041200), one(0177700), "$s", m68000up | mcf }, +{"clrb", one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, +{"clrw", one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, +{"clrl", one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, {"cmp2b", two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2w", two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2l", two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmpaw", one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcf }, +{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpib", one(0006000), one(0177700), "#b@s", m68000up }, -{"cmpib", one(0006000), one(0177700), "#bDs", mcfv4up }, +{"cmpib", one(0006000), one(0177700), "#bDs", mcfisa_b }, {"cmpiw", one(0006100), one(0177700), "#w@s", m68000up }, -{"cmpiw", one(0006100), one(0177700), "#wDs", mcfv4up }, +{"cmpiw", one(0006100), one(0177700), "#wDs", mcfisa_b }, {"cmpil", one(0006200), one(0177700), "#l@s", m68000up }, -{"cmpil", one(0006200), one(0177700), "#lDs", mcf }, +{"cmpil", one(0006200), one(0177700), "#lDs", mcfisa_a }, {"cmpmb", one(0130410), one(0170770), "+s+d", m68000up }, {"cmpmw", one(0130510), one(0170770), "+s+d", m68000up }, @@ -276,20 +276,20 @@ const struct m68k_opcode m68k_opcodes[] = /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ {"cmpb", one(0006000), one(0177700), "#b@s", m68000up }, -{"cmpb", one(0006000), one(0177700), "#bDs", mcfv4up }, +{"cmpb", one(0006000), one(0177700), "#bDs", mcfisa_b }, {"cmpb", one(0130410), one(0170770), "+s+d", m68000up }, {"cmpb", one(0130000), one(0170700), ";bDd", m68000up }, -{"cmpb", one(0130000), one(0170700), "*bDd", mcfv4up }, +{"cmpb", one(0130000), one(0170700), "*bDd", mcfisa_b }, {"cmpw", one(0130300), one(0170700), "*wAd", m68000up }, {"cmpw", one(0006100), one(0177700), "#w@s", m68000up }, -{"cmpw", one(0006100), one(0177700), "#wDs", mcfv4up }, +{"cmpw", one(0006100), one(0177700), "#wDs", mcfisa_b }, {"cmpw", one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpw", one(0130100), one(0170700), "*wDd", m68000up | mcfv4up }, -{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcf }, +{"cmpw", one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b }, +{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpl", one(0006200), one(0177700), "#l@s", m68000up }, -{"cmpl", one(0006200), one(0177700), "#lDs", mcf }, +{"cmpl", one(0006200), one(0177700), "#lDs", mcfisa_a }, {"cmpl", one(0130610), one(0170770), "+s+d", m68000up }, -{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcf }, +{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, {"dbcc", one(0052310), one(0177770), "DsBw", m68000up }, {"dbcs", one(0052710), one(0177770), "DsBw", m68000up }, @@ -308,20 +308,20 @@ const struct m68k_opcode m68k_opcodes[] = {"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, {"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, -{"divsw", one(0100700), one(0170700), ";wDd", m68000up | mcf5206eup }, +{"divsw", one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD", mcf5206eup }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, {"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divuw", one(0100300), one(0170700), ";wDd", m68000up | mcf5206eup }, +{"divuw", one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD", mcf5206eup }, +{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, @@ -331,7 +331,7 @@ const struct m68k_opcode m68k_opcodes[] = {"eoriw", one(0005100), one(0177700), "#w$s", m68000up }, {"eoriw", one(0005174), one(0177777), "#wSs", m68000up }, {"eoril", one(0005200), one(0177700), "#l$s", m68000up }, -{"eoril", one(0005200), one(0177700), "#lDs", mcf }, +{"eoril", one(0005200), one(0177700), "#lDs", mcfisa_a }, {"eori", one(0005074), one(0177777), "#bCs", m68000up }, {"eori", one(0005174), one(0177777), "#wSs", m68000up }, {"eori", one(0005100), one(0177700), "#w$s", m68000up }, @@ -344,8 +344,8 @@ const struct m68k_opcode m68k_opcodes[] = {"eorw", one(0005174), one(0177777), "#wSs", m68000up }, {"eorw", one(0130500), one(0170700), "Dd$s", m68000up }, {"eorl", one(0005200), one(0177700), "#l$s", m68000up }, -{"eorl", one(0005200), one(0177700), "#lDs", mcf }, -{"eorl", one(0130600), one(0170700), "Dd$s", m68000up | mcf }, +{"eorl", one(0005200), one(0177700), "#lDs", mcfisa_a }, +{"eorl", one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"eor", one(0005074), one(0177777), "#bCs", m68000up }, {"eor", one(0005174), one(0177777), "#wSs", m68000up }, {"eor", one(0005100), one(0177700), "#w$s", m68000up }, @@ -356,11 +356,11 @@ const struct m68k_opcode m68k_opcodes[] = {"exg", one(0140610), one(0170770), "DdAs", m68000up }, {"exg", one(0140610), one(0170770), "AsDd", m68000up }, -{"extw", one(0044200), one(0177770), "Ds", m68000up|mcf }, -{"extl", one(0044300), one(0177770), "Ds", m68000up|mcf }, -{"extbl", one(0044700), one(0177770), "Ds", m68020up|cpu32|mcf }, +{"extw", one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, +{"extl", one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, +{"extbl", one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a }, -{"ff1", one(0002300), one(0177770), "Ds", mcf528x}, +{"ff1", one(0002300), one(0177770), "Ds", mcfisa_aa}, /* float stuff starts here */ @@ -1419,28 +1419,28 @@ const struct m68k_opcode m68k_opcodes[] = {"ftwotoxx", two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"halt", one(0045310), one(0177777), "", m68060 | mcf }, +{"halt", one(0045310), one(0177777), "", m68060 | mcfisa_a }, -{"illegal", one(0045374), one(0177777), "", m68000up | mcf }, -{"intouch", one(0xf428), one(0xfff8), "As", mcfv4eup }, +{"illegal", one(0045374), one(0177777), "", m68000up | mcfisa_a }, +{"intouch", one(0xf428), one(0xfff8), "As", mcfisa_b }, -{"jmp", one(0047300), one(0177700), "!s", m68000up | mcf }, +{"jmp", one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, -{"jra", one(0060000), one(0177400), "Bg", m68000up | mcf }, -{"jra", one(0047300), one(0177700), "!s", m68000up | mcf }, +{"jra", one(0060000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jra", one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, -{"jsr", one(0047200), one(0177700), "!s", m68000up | mcf }, +{"jsr", one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, -{"jbsr", one(0060400), one(0177400), "Bg", m68000up | mcf }, -{"jbsr", one(0047200), one(0177700), "!s", m68000up | mcf }, +{"jbsr", one(0060400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jbsr", one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, -{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcf }, +{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, {"lpstop", two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 }, -{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcf }, +{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, {"linkl", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, -{"link", one(0047120), one(0177770), "As#W", m68000up | mcf }, +{"link", one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, {"link", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, {"lslb", one(0160410), one(0170770), "QdDs", m68000up }, @@ -1448,16 +1448,16 @@ const struct m68k_opcode m68k_opcodes[] = {"lslw", one(0160510), one(0170770), "QdDs", m68000up }, {"lslw", one(0160550), one(0170770), "DdDs", m68000up }, {"lslw", one(0161700), one(0177700), "~s", m68000up }, -{"lsll", one(0160610), one(0170770), "QdDs", m68000up | mcf }, -{"lsll", one(0160650), one(0170770), "DdDs", m68000up | mcf }, +{"lsll", one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"lsll", one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, {"lsrb", one(0160010), one(0170770), "QdDs", m68000up }, {"lsrb", one(0160050), one(0170770), "DdDs", m68000up }, {"lsrw", one(0160110), one(0170770), "QdDs", m68000up }, {"lsrw", one(0160150), one(0170770), "DdDs", m68000up }, {"lsrw", one(0161300), one(0177700), "~s", m68000up }, -{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf }, -{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf }, +{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, {"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0800), "uMum", mcfmac }, {"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0b00), "uMumiI", mcfmac }, @@ -1504,13 +1504,13 @@ const struct m68k_opcode m68k_opcodes[] = jtc@cygnus.com - 97/01/24 */ -{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf }, -{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf }, +{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, {"movclrl", one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, -{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf }, -{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf }, +{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, +{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, {"movec", one(0047172), one(0177777), "JjR1", m68010up }, {"movec", one(0047172), one(0177777), "#jR1", m68010up }, @@ -1525,60 +1525,60 @@ const struct m68k_opcode m68k_opcodes[] = {"moveml", one(0046300), one(0177700), "