From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 7 Aug 2019 06:17:44 +0000 (+0200)
Subject: cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
X-Git-Tag: 24jan2021_ls180~1067
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b7ca0cff7cae7452656b3e06f0d63b347ab8699;p=litex.git

cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index a15c2ec1..ed07b871 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -64,7 +64,7 @@ class XilinxClocking(Module, AutoCSR):
         config = {}
         for divclk_divide in range(*self.divclk_divide_range):
             config["divclk_divide"] = divclk_divide
-            for clkfbout_mult in range(*self.clkfbout_mult_frange):
+            for clkfbout_mult in reversed(range(*self.clkfbout_mult_frange)):
                 all_valid = True
                 vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
                 (vco_freq_min, vco_freq_max) = self.vco_freq_range