From: Hoa Nguyen <hoanguyen@ucdavis.edu>
Date: Fri, 1 Mar 2019 02:26:07 +0000 (-0800)
Subject: tests: add riscv to cpu tests
X-Git-Tag: v19.0.0.0~969
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b81e087c239e74a84405805bc8a3f6f3c1798a4;p=gem5.git

tests: add riscv to cpu tests

Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index 6fb68a9db..f34b23d07 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -38,6 +38,7 @@ workloads = ('Bubblesort','FloatMM')
 valid_isas = {
     'x86': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'DerivO3CPU'),
     'arm': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
+    'riscv': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
 }