From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue, 28 Jun 2022 10:07:52 +0000 (+0900)
Subject: RISC-V: Improve "bits undefined" diagnostics
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b84c098e533f87d7973fd6fe8a39ee97255ebdb;p=binutils-gdb.git

RISC-V: Improve "bits undefined" diagnostics

This commit improves internal error message
"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"
to display actual unused bits (excluding non-instruction bits).

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Exclude non-
	instruction bits from displaying internal diagnostics.
	Change error message slightly.
---

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 70558796c24..3237369f11f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1398,8 +1398,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
   if (used_bits != required_bits)
     {
       as_bad (_("internal: bad RISC-V opcode "
-		"(bits 0x%lx undefined): %s %s"),
-	      ~(unsigned long)(used_bits & required_bits),
+		"(bits %#llx undefined or invalid): %s %s"),
+	      (unsigned long long)(used_bits ^ required_bits),
 	      opc->name, opc->args);
       return false;
     }