From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 4 Sep 2020 19:56:44 +0000 (+0100)
Subject: add UART reserved IRQ @ 0
X-Git-Tag: semi_working_ecp5~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b85a4cdca82b820697ee07ac01d37673e26528d;p=soc.git

add UART reserved IRQ @ 0
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 69a497b4..475314f2 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -37,6 +37,7 @@ class LibreSoCSim(SoCSDRAM):
             #sdram_data_width      = 16,
             #sdram_module          = "MT48LC16M16",
             sdram_data_width      = 16,
+            irq_reserved_irqs = {'uart': 0},
             ):
         assert cpu in ["libresoc", "microwatt"]
         platform     = Platform()
@@ -58,10 +59,10 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = None
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
-        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-        #            "tests/xics/xics.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "hello_world/hello_world.bin"
+                    "tests/xics/xics.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "hello_world/hello_world.bin"
 
         # reserve XICS ICP and XICS memory addresses.
         # TODO: not have these conflict with csr locations