From: Gabe Black <gabeblack@google.com>
Date: Tue, 16 Apr 2019 03:47:48 +0000 (-0700)
Subject: python: Replace the Master/Slave Ports with Request/Response ports.
X-Git-Tag: v19.0.0.0~929
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b87ee1e1f481e78170230fa7548f1b177d13e8c;p=gem5.git

python: Replace the Master/Slave Ports with Request/Response ports.

These are a little more descriptive and a little less potentially
offensive.

Change-Id: I84c30f783f0a4c242cb4f54ab272b6fdf1e9eec7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 60d4a14b9..8b0a14af3 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -2099,17 +2099,18 @@ class Port(object):
     def cxx_decl(self, code):
         code('unsigned int port_${{self.name}}_connection_count;')
 
-Port.compat('MASTER', 'SLAVE')
+Port.compat('GEM5 REQUESTER', 'GEM5 RESPONDER')
 
-class MasterPort(Port):
-    # MasterPort("description")
+class RequestPort(Port):
+    # RequestPort("description")
     def __init__(self, desc):
-        super(MasterPort, self).__init__('MASTER', desc, is_source=True)
+        super(RequestPort, self).__init__(
+                'GEM5 REQUESTER', desc, is_source=True)
 
-class SlavePort(Port):
-    # SlavePort("description")
+class ResponsePort(Port):
+    # ResponsePort("description")
     def __init__(self, desc):
-        super(SlavePort, self).__init__('SLAVE', desc)
+        super(ResponsePort, self).__init__('GEM5 RESPONDER', desc)
 
 # VectorPort description object.  Like Port, but represents a vector
 # of connections (e.g., as on a XBar).
@@ -2122,15 +2123,22 @@ class VectorPort(Port):
     def makeRef(self, simobj):
         return VectorPortRef(simobj, self.name, self.role, self.is_source)
 
-class VectorMasterPort(VectorPort):
-    # VectorMasterPort("description")
+class VectorRequestPort(VectorPort):
+    # VectorRequestPort("description")
     def __init__(self, desc):
-        super(VectorMasterPort, self).__init__('MASTER', desc, is_source=True)
+        super(VectorRequestPort, self).__init__(
+                'GEM5 REQUESTER', desc, is_source=True)
 
-class VectorSlavePort(VectorPort):
-    # VectorSlavePort("description")
+class VectorResponsePort(VectorPort):
+    # VectorResponsePort("description")
     def __init__(self, desc):
-        super(VectorSlavePort, self).__init__('SLAVE', desc)
+        super(VectorResponsePort, self).__init__('GEM5 RESPONDER', desc)
+
+# Old names, maintained for compatibility.
+MasterPort = RequestPort
+SlavePort = ResponsePort
+VectorMasterPort = VectorRequestPort
+VectorSlavePort = VectorResponsePort
 
 # 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
 # proxy objects (via set_param_desc()) so that proxy error messages
@@ -2164,5 +2172,6 @@ __all__ = ['Param', 'VectorParam',
            'MaxAddr', 'MaxTick', 'AllMemory',
            'Time',
            'NextEthernetAddr', 'NULL',
-           'Port', 'MasterPort', 'SlavePort',
-           'VectorPort', 'VectorMasterPort', 'VectorSlavePort']
+           'Port', 'RequestPort', 'ResponsePort', 'MasterPort', 'SlavePort',
+           'VectorPort', 'VectorRequestPort', 'VectorResponsePort',
+           'VectorMasterPort', 'VectorSlavePort']