From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 17:25:47 +0000 (+0100)
Subject: make MultiCompUnit and testing ALU use regspec API and nmutil pipeline API
X-Git-Tag: div_pipeline~909
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6b97eff4a06f40a0db0d4fd47fcc2f04df42b353;p=soc.git

make MultiCompUnit and testing ALU use regspec API and nmutil pipeline API
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index af373ca3..29c97d7d 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -84,7 +84,10 @@ class Dummy:
 class ALU(Elaboratable):
     def __init__(self, width):
         self.p = Dummy() # make look like nmutil pipeline API
+        self.p.data_i = Dummy()
+        self.p.data_i.ctx = Dummy()
         self.n = Dummy() # make look like nmutil pipeline API
+        self.n.data_o = Dummy()
         self.p.valid_i = Signal()
         self.p.ready_o = Signal()
         self.n.ready_i = Signal()
@@ -99,6 +102,11 @@ class ALU(Elaboratable):
         self.out = Array([Signal(width)])
         self.o = self.out[0]
         self.width = width
+        # more "look like nmutil pipeline API"
+        self.p.data_i.ctx.op = self.op
+        self.p.data_i.a = self.a
+        self.p.data_i.b = self.b
+        self.n.data_o.o = self.o
 
     def elaborate(self, platform):
         m = Module()
diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 7cdd19d0..89e4c6ee 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -199,6 +199,24 @@ class MultiCompUnit(Elaboratable):
         self.data_o = self.dest[0] # Dest out
         self.done_o = cu.done_o
 
+    def get_out(self, i):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.out[i]
+        # regspec-based API: look up variable through regspec according to row number
+        print ("get out", dir(self.alu.n.data_o))
+        return getattr(self.alu.n.data_o, self.rwid[1][i][1])
+
+    def get_in(self, i):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.i[i]
+        # regspec-based API: look up variable through regspec according to row number
+        print ("get in", dir(self.alu.p.data_i))
+        return getattr(self.alu.p.data_i, self.rwid[0][i][1])
+
+    def get_op(self):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.op
+        return self.alu.p.data_i.ctx.op
     def elaborate(self, platform):
         m = Module()
         m.submodules.alu = self.alu
@@ -262,11 +280,11 @@ class MultiCompUnit(Elaboratable):
         for i in range(self.n_dst):
             name = "data_r%d" % i
             data_r = Signal(self.cu._get_srcwid(i), name=name, reset_less=True)
-            latchregister(m, self.alu.out[i], data_r, req_l.q[i], name)
+            latchregister(m, self.get_out(i), data_r, req_l.q[i], name)
             drl.append(data_r)
 
         # pass the operation to the ALU
-        m.d.comb += self.alu.op.eq(oper_r)
+        m.d.comb += self.get_op().eq(oper_r)
 
         # create list of src/alu-src/src-latch.  override 1st and 2nd one below.
         # in the case, for ALU and Logical pipelines, we assume RB is the 2nd operand
@@ -274,7 +292,7 @@ class MultiCompUnit(Elaboratable):
         # TODO: assume RA is the 1st operand, zero_a detection is needed.
         sl = []
         for i in range(self.n_src):
-            sl.append([self.src_i[i], self.alu.i[i], src_l.q[i]])
+            sl.append([self.src_i[i], self.get_in(i), src_l.q[i]])
 
         # if the operand subset has "zero_a" we implicitly assume that means
         # src_i[0] is an INT register type where zero can be multiplexed in, instead.