From: Carl Love Date: Fri, 26 Mar 2021 21:54:47 +0000 (-0500) Subject: RS6000 Add support to print vector register contents as float128 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ba4cb845bd319f11d1caf42de5156daed28ff9d;p=binutils-gdb.git RS6000 Add support to print vector register contents as float128 This patch adds a floating point 128-bit composite field to the vsx register type. When printing the register with p/f the float128 field will be printed as a 128-bit floating point value. A test case to verify the new vsx register field is visible and correctly prints out the value of a 128-bit floating point value is also added. gdb/ChangeLog: * rs6000-tdep.c (rs6000_builtin_type_vec128): Add t_float128 variable. (rs6000_builtin_type_vec128): Add append_composite_type_field for float128. gdb/testsuite/ChangeLog: * gdb.arch/vsx-vsr-float128.c: New test file. * gdb.arch/vsx-vsr-float128.exp: New expect file. --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index c363dc9091c..67a3b6cff44 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,9 @@ +2021-4-12 Carl Love + + * rs6000-tdep.c (rs6000_builtin_type_vec128): Add t_float128 variable. + (rs6000_builtin_type_vec128): Add append_composite_type_field for + float128. + 2021-04-12 Simon Marchi * nat/windows-nat.c: Remove all code guarded by _WIN32_WCE. diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index cb06cd952a7..276b4fa5583 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -2355,6 +2355,7 @@ rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) /* The type we're building is this type = union __ppc_builtin_type_vec128 { + float128_t float128; uint128_t uint128; double v2_double[2]; float v4_float[4]; @@ -2364,10 +2365,15 @@ rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) } */ + /* PPC specific type for IEEE 128-bit float field */ + struct type *t_float128 + = arch_float_type (gdbarch, 128, "float128_t", floatformats_ia64_quad); + struct type *t; t = arch_composite_type (gdbarch, "__ppc_builtin_type_vec128", TYPE_CODE_UNION); + append_composite_type_field (t, "float128", t_float128); append_composite_type_field (t, "uint128", bt->builtin_uint128); append_composite_type_field (t, "v2_double", init_vector_type (bt->builtin_double, 2)); diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index aae2aa8384c..f833782555d 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2021-4-12 Carl Love + + * gdb.arch/vsx-vsr-float128.c: New test file. + * gdb.arch/vsx-vsr-float128.exp: New expect file. + 2021-04-12 Markus Metzger * gdb.btrace/reconnect.exp: Relax expected stepi output. diff --git a/gdb/testsuite/gdb.arch/vsx-vsr-float28.c b/gdb/testsuite/gdb.arch/vsx-vsr-float28.c new file mode 100644 index 00000000000..8e1f88afb15 --- /dev/null +++ b/gdb/testsuite/gdb.arch/vsx-vsr-float28.c @@ -0,0 +1,31 @@ +/* This file is part of GDB, the GNU debugger. + + Copyright 2008-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include + +int +main () +{ + __float128 x, y, z; + + x = -2.25; + y = 3.5; + z = x * y; + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/vsx-vsr-float28.exp b/gdb/testsuite/gdb.arch/vsx-vsr-float28.exp new file mode 100644 index 00000000000..cefe43ccab7 --- /dev/null +++ b/gdb/testsuite/gdb.arch/vsx-vsr-float28.exp @@ -0,0 +1,90 @@ +# Copyright (C) 2008-2021 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +# +# Test the vsr registers print values in float128 bit format. +# + + +if {![istarget "powerpc*"] || [skip_vsx_tests]} then { + verbose "Skipping vsr float128 field tests." + return +} + +standard_testfile + +set compile_flags {debug nowarnings quiet} +if [get_compiler_info] { + warning "get_compiler failed" + return -1 +} + +if [test_compiler_info gcc*] { + set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" +} elseif [test_compiler_info xlc*] { + set compile_flags "$compile_flags additional_flags=-qaltivec" +} else { + warning "unknown compiler" + return -1 +} + +if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { + untested "failed to compile" + return -1 +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Run to `main' where we begin our tests. + +if ![runto_main] then { + fail "can't run to main" + return 0 +} + +set endianness [get_endianness] + +# Data sets used throughout the test + +set vector_field ".*float128 = -2.25,.*" + +# The vsx registers now contain a 128-bit floating point field. The following tests +# setting a vsr register with a 128-bit floating point value and then printing the +# register contents using the float format to verify the value is correctly printed +# as a 128-bit value. + +# the following corresponds to a 128-bit float value of -2.25 +if {$endianness == "big"} { + gdb_test_no_output "set \$vs1.v4_int32\[3\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[2\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[1\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[0\] = 0xc0002000" +} else { + gdb_test_no_output "set \$vs1.v4_int32\[0\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[1\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[2\] = 0x0" + gdb_test_no_output "set \$vs1.v4_int32\[3\] = 0xc0002000" +} + +# check the contents of the register +gdb_test "p/f \$vs1" "$vector_field" + +gdb_exit + + +