From: lkcl Date: Thu, 11 Aug 2022 23:13:08 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~890 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ba88be405af6282263335ba01cbf1a6ff6e18ff;p=libreriscv.git --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index ea76a173a..57d07490e 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -22,8 +22,7 @@ [^8]: LD/ST Fault-First: see [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf) [^9]: Data-dependent Fail-First: Based on LD/ST Fail-first, extended to data. Truncates VL based on failing Rc=1 test. Similar to Z80 CPIR. See [[sv/svp64/appendix]] [^10]: Predicate-result effectively turns any standard op into a type of "cmp". See [[sv/svp64/appendix]] -[^11]: Any non-power-of-two Matrices up to 127 FMACs (or other FMA-style op -including Ternary Logical), full triple-loop Schedule. See [[sv/remap]] +[^11]: Any non-power-of-two Matrices up to 127 FMACs or other FMA-style op including Ternary Logical, full triple-loop Schedule. See [[sv/remap]] [^12]: DCT (Lee) and FFT Full Triple-loops supported, RADIX2-only. Normally only found in VLIW DSPs (TI MSP320, Qualcom Hexagon). See [[sv/remap]] [^v2]: VSX's Vector Registers are mis-named: they are 100% PackedSIMD. AVX-512 is not a Vector ISA either. See [Flynn's Taxonomy](https://en.wikipedia.org/wiki/Flynn%27s_taxonomy) [^v3]: Power ISA v3.1 contains "Matrix Multiply Assist" (MMA) which due to PackedSIMD is restricted to RADIX2 and requires inline assembler loop-unrolling for non-power-of-two Matrix dimensions