From: Jason Ekstrand Date: Wed, 15 Mar 2017 18:58:52 +0000 (-0700) Subject: anv: Flush caches prior to PIPELINE_SELECT on all gens X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6baae9625d26d282a72481598f9431fcad3211f6;p=mesa.git anv: Flush caches prior to PIPELINE_SELECT on all gens The programming note that says we need to do this still exists in the SkyLake PRM and, from looking at the bspec, seems like it may apply to all hardware generations SNB+. Unfortunately, this isn't particularly clear cut since there is also language in the bspec that says you can skip the flushing and stall to get better throughput. Experimentation with the "Car Chase" benchmark in GL seems to indicate that some form of flushing is still needed. This commit makes us do the full set of flushes regardless of hardware generation. We can always reduce the flushing later. Reported-by: Topi Pohjolainen Reviewed-by: Iago Toral Quiroga Cc: "17.0 13.0" --- diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5d923a8c08d..d0ddc29f008 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2133,8 +2133,8 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer, */ if (pipeline == GPGPU) anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t); +#endif -#elif GEN_GEN <= 7 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] * PIPELINE_SELECT [DevBWR+]": * @@ -2160,7 +2160,6 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer, pc.InstructionCacheInvalidateEnable = true; pc.PostSyncOperation = NoWrite; } -#endif } void