From: Bas Nieuwenhuizen Date: Tue, 15 Aug 2017 16:09:21 +0000 (+0200) Subject: radv: Implement bc optimize. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bafb56df69b5804dd113d24285312f266cadae2;p=mesa.git radv: Implement bc optimize. Seems like we actually enabled it already, but did not implement the shader part. With this patch we do. Reviewed-by: Nicolai Hähnle Reviewed-by: Dave Airlie --- diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 88f2203316c..846840b7b06 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -5009,10 +5009,39 @@ handle_vs_inputs(struct nir_to_llvm_context *ctx, handle_vs_input_decl(ctx, variable); } +static void +prepare_interp_optimize(struct nir_to_llvm_context *ctx, + struct nir_shader *nir) +{ + if (!ctx->options->key.fs.multisample) + return; + + bool uses_center = false; + bool uses_centroid = false; + nir_foreach_variable(variable, &nir->inputs) { + if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT || + variable->data.sample) + continue; + + if (variable->data.centroid) + uses_centroid = true; + else + uses_center = true; + } + + if (uses_center && uses_centroid) { + LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, ""); + ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, ""); + ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, ""); + } +} + static void handle_fs_inputs(struct nir_to_llvm_context *ctx, struct nir_shader *nir) { + prepare_interp_optimize(ctx, nir); + nir_foreach_variable(variable, &nir->inputs) handle_fs_input_decl(ctx, variable); diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index 376db1387a4..53ea238c3c9 100644 --- a/src/amd/common/ac_nir_to_llvm.h +++ b/src/amd/common/ac_nir_to_llvm.h @@ -60,6 +60,7 @@ struct ac_fs_variant_key { uint32_t col_format; uint32_t is_int8; uint32_t is_int10; + uint32_t multisample : 1; }; union ac_shader_variant_key { diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index bd5eeb776c4..75371a0be5a 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2069,6 +2069,9 @@ radv_pipeline_init(struct radv_pipeline *pipeline, if (modules[MESA_SHADER_FRAGMENT]) { union ac_shader_variant_key key = {0}; key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format; + if (pCreateInfo->pMultisampleState && + pCreateInfo->pMultisampleState->rasterizationSamples > 1) + key.fs.multisample = true; if (pipeline->device->physical_device->rad_info.chip_class < VI) radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);