From: Chris Forbes Date: Tue, 8 Oct 2013 08:42:10 +0000 (+1300) Subject: i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bb2cf2107c4461ea9dd100edaf110b839311b90;p=mesa.git i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes Reviewed-by: Ian Romanick --- diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 5ba9d45c9e8..d8224878574 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -771,6 +771,7 @@ enum opcode { SHADER_OPCODE_TXF_MS, SHADER_OPCODE_LOD, SHADER_OPCODE_TG4, + SHADER_OPCODE_TG4_OFFSET, SHADER_OPCODE_SHADER_TIME_ADD, diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a3268fb73bf..b724dca4f60 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -756,6 +756,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst) case SHADER_OPCODE_TXF: case SHADER_OPCODE_TXF_MS: case SHADER_OPCODE_TG4: + case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_TXL: case SHADER_OPCODE_TXS: case SHADER_OPCODE_LOD: diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index df72b989066..6b9f70b5693 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -438,6 +438,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src assert(brw->gen >= 6); msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4; break; + case SHADER_OPCODE_TG4_OFFSET: + assert(brw->gen >= 7); + msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; + break; default: assert(!"not reached"); break; @@ -551,7 +555,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src } } - uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4 + uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 || + inst->opcode == SHADER_OPCODE_TG4_OFFSET) ? c->prog_data.base.binding_table.gather_texture_start : c->prog_data.base.binding_table.texture_start) + inst->sampler; @@ -1520,6 +1525,7 @@ fs_generator::generate_code(exec_list *instructions) case SHADER_OPCODE_TXS: case SHADER_OPCODE_LOD: case SHADER_OPCODE_TG4: + case SHADER_OPCODE_TG4_OFFSET: generate_tex(inst, dst, src[0]); break; case FS_OPCODE_DDX: diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index bb5380fdbf8..2fb43a6b4e6 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -443,6 +443,8 @@ brw_instruction_name(enum opcode op) return "txf_ms"; case SHADER_OPCODE_TG4: return "tg4"; + case SHADER_OPCODE_TG4_OFFSET: + return "tg4_offset"; case FS_OPCODE_DDX: return "ddx"; @@ -539,7 +541,8 @@ backend_instruction::is_tex() opcode == SHADER_OPCODE_TXL || opcode == SHADER_OPCODE_TXS || opcode == SHADER_OPCODE_LOD || - opcode == SHADER_OPCODE_TG4); + opcode == SHADER_OPCODE_TG4 || + opcode == SHADER_OPCODE_TG4_OFFSET); } bool diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 9cbbae0212a..e333c6b6ed1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -274,6 +274,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst) case SHADER_OPCODE_TXF_MS: case SHADER_OPCODE_TXS: case SHADER_OPCODE_TG4: + case SHADER_OPCODE_TG4_OFFSET: return inst->header_present ? 1 : 0; default: assert(!"not reached"); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index 5196feb28e5..f4f2bcc71f7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -311,6 +311,9 @@ vec4_generator::generate_tex(vec4_instruction *inst, case SHADER_OPCODE_TG4: msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4; break; + case SHADER_OPCODE_TG4_OFFSET: + msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; + break; default: assert(!"should not get here: invalid VS texture opcode"); break; @@ -385,7 +388,8 @@ vec4_generator::generate_tex(vec4_instruction *inst, break; } - uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4 + uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 || + inst->opcode == SHADER_OPCODE_TG4_OFFSET) ? prog_data->base.binding_table.gather_texture_start : prog_data->base.binding_table.texture_start) + inst->sampler; @@ -1096,6 +1100,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case SHADER_OPCODE_TXL: case SHADER_OPCODE_TXS: case SHADER_OPCODE_TG4: + case SHADER_OPCODE_TG4_OFFSET: generate_tex(inst, dst, src[0]); break;