From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 19:02:28 +0000 (-0800)
Subject: Make TimingInfo::TimingInfo(SigBit) constructor explicit
X-Git-Tag: working-ls180~780^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bb3d9f9c09993960a5a91fa51f163a7e67e2503;p=yosys.git

Make TimingInfo::TimingInfo(SigBit) constructor explicit
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index dc0f997fe..402f41597 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -263,7 +263,7 @@ struct XAigerWriter
 						continue;
 
 					for (int i = 0; i < GetSize(conn.second); i++) {
-						auto d = t.at(SigBit(port_wire,i), 0);
+						auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
 						if (d == 0)
 							continue;
 
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 8d0904175..7855ddd15 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -31,8 +31,9 @@ struct TimingInfo
 	{
 		RTLIL::IdString name;
 		int offset;
-		NameBit() {}
-		NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+		NameBit() : offset(0) {}
+		NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
+		explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
 		bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
 		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
 		unsigned int hash() const { return mkhash_add(name.hash(), offset); }
@@ -127,7 +128,7 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &d : dst) {
-					auto &v = t.arrival[d];
+					auto &v = t.arrival[NameBit(d)];
 					v = std::max(v, max);
 				}
 			}
@@ -151,7 +152,7 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &s : src) {
-					auto &v = t.required[s];
+					auto &v = t.required[NameBit(s)];
 					v = std::max(v, max);
 				}
 			}
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e5de2bcc4..e46ad0a02 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -440,7 +440,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
 			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
 			for (int i = 0; i < GetSize(conn.second); i++) {
-				auto d = t.at(SigBit(port_wire,i), 0);
+				auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
 				if (d == 0)
 					continue;
 
@@ -582,7 +582,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					else
 						ss << " ";
 					log_assert(GetSize(wire) == 1);
-					auto it = t.find(SigBit(wire,0));
+					auto it = t.find(TimingInfo::NameBit(port_name,0));
 					if (it == t.end())
 						// Assume that no setup time means zero
 						ss << 0;
@@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					first = false;
 				else
 					ss << " ";
-				auto jt = t.find(std::make_pair(i,o));
+				auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o)));
 				if (jt == t.end())
 					ss << "-";
 				else